ST72361AR4-Auto datasheet(46/279 Pages) STMICROELECTRONICS

46 / 279 page

Supply, reset and clock management

ST72361xx-Auto

46/279

Doc ID 12468 Rev 3

5.6.5

System integrity (SI) control/status register (SICSR)

Read/Write

Reset value: 000x 000x (00h)

Bit 7 = Reserved, must be kept cleared.

Bit 6 = AVDIE Voltage Detector interrupt enable

This bit is set and cleared by software. It enables an interrupt to be generated when the

AVDF flag changes (toggles). The pending interrupt information is automatically cleared

when software enters the AVD interrupt routine.

0: AVD interrupt disabled

1: AVD interrupt enabled

Bit 5 = AVDF Voltage Detector flag

This read-only bit is set and cleared by hardware. If the AVDIE bit is set, an interrupt request

is generated when the AVDF bit changes value. Refer to Figure 16 and to Monitoring the

VDD main supply for additional details.

0: VDD over VIT+(AVD) threshold

1: VDD under VIT-(AVD) threshold

Bit 4 = LVDRF LVD reset flag

This bit indicates that the last Reset was generated by the LVD block. It is set by hardware

(LVD reset) and cleared by software (writing zero). See WDGRF flag description for more

details. When the LVD is disabled by OPTION BYTE, the LVDRF bit value is undefined.

Bits 3:1 = Reserved, must be kept cleared.

Bit 0 = WDGRF Watchdog reset flag

This bit indicates that the last Reset was generated by the Watchdog peripheral. It is set by

hardware (watchdog reset) and cleared by software (writing zero) or an LVD Reset (to

ensure a stable cleared state of the WDGRF flag when CPU starts). Combined with the

LVDRF flag information, the flag description is given by the following table.

AVDIE

AVDF

LVDRF

WDGRF

ST72361AR4-Auto Datasheet(PDF) 46 Page - STMicroelectronics