10

ICS950812

0542G—08/21/03

Table 3

PCI_STOP# I

Note: When this Byte 0, Bit 3 is low (0), all PCI clocks are stopped.

Table 4

CPUCLKT/C (2:0) Outputs I

Note: Individual CPUCLK outputs are controlled by Byte 1, Bit 3, 4, and 5.

Table 5

PCICLK_F (2:0) Outputs I

Note: Individual PCICLK outputs are controlled by Byte 3, Bit 3, 4, and 5.

Table 6

3V66 (5:2)/66MHz_OUT(2:0)/66MHz_IN I

Note: Activating Byte 5, Bit 5 will allow CPU_STOP# to control stop of pins 21, 22, 23, and 24.

CPU_STOP#

(Pin 53)

Byte 5

Bit 5

3V66 (5:2) (Driven)

66MHZ_OUT(2:0)/66MHZ_IN (Buffered)

01

10

1`

1

Byte 0, Bit 3 Read Bit

(Internal Status)

0

0

0

1

PCI_STOP#

(Pin 34)

CPU_STOP#

(Pin 53)

Byte 1

Bit 3, 4, 5

Byte 0 Bit 3

Write Bit

00

CPUCLKT/C (2:0) Outputs

00

Stop

0

1

Running

1

0

Running

1

1

Running

PCI_STOP#

(Pin 34)

Byte 3

Bit 3, 4, 5

PCICLK (2:0) Outputs

00

Stop

0

1

Running

1

0

Running

1

1

Running

Running

Running

00

01

Running

Stopped

10

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