TAS3001CPWR datasheet(14/56 Pages) TI

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1.12 Pin Functions

TERMINAL

I/O

DESCRIPTION

NAME

NO.

I/O

DESCRIPTION

AVDD_PLL

Analog power supply for the PLL

AVSS_PLL

Analog ground for the PLL

CAP_PLL

C1 = 1500 pF // R1 = 27

Ω + C2 = 0.068 µF (recommended)

CS1

I2C address bit A0; low = 0, high = 1

CS2

I2C address bit A1; low = 0, high = 1

DVDD

Digital power supply

DVSS

Digital ground

LRCLK

I2S left/right clock sampling frequency (fs)

LRCLKOUT

LRCLK generated from input MCLK (usually 256 fs) − normally routed on PCB to pin 10

(LRCLK) as input fs sample clock.

MCLK

Master clock (256 x fs)

17, 18, 20−22,

25, 26

Reserved − No connection for normal operation

POWERDOWN

Powerdown input

RESET

Reset, high = normal operation, low = reinitialize the device

RESERVED

15, 27

Reserved − digital ground for normal operation

SCL

I/O

Slave serial I2C clock

SCLK

Shift clock (bit clock)

SCLKOUT

SCLK generated from input MCLK (usually 256 fs) − normally routed on PCB to pin 11 (SCLK)

as input 64 fs bit clock.

SDA

I/O

Slave serial I2C data

SDIN1

Serial audio data input one

SDIN2

Serial audio data input two

SDOUT

Serial audio data output

NOTE: Reset and other control functions require MCLK to be running. The system reset operation is a synchronous operation and requires a

minimum of four MCLK cycles to reset the device.

1.13 Ordering Information

PACKAGE

SMALL OUTLINE (PW)

°C to 70°C

TAS3001CPW

1.14 Power Supply

•

Digital supply voltage—DVDD, DVSS of 3.3 V

•

Analog supply voltage—AVDD−PLL, AVSS−PLL of 3.3 V

NOTE: AVDD and AVSS for the PLL are derived from the digital supply and digital ground.

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