MPM3686 – 18V 20A STEP-DOWN POWER MODULE

MPM3686 Rev. 1.02

www.MonolithicPower.com

14

10/13/2016

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Figure 6

Soft Start

The MPM3686 employs a soft start (SS)

mechanism to ensure a smooth output during

power-up. When the EN pin goes high, an

internal current source (20μA) charges the SS

capacitor. The SS capacitor voltage takes over

the REF voltage to the PWM comparator. The

output voltage smoothly ramps up with the SS

voltage. Once the SS voltage reaches the REF

over the PWM comparator. At this point, soft start

finishes and the device enters steady state

operation.

An internal 100nF SS capacitor is used. So the

default (with SS pin floating) SS time can be

estimated as:

REF

SS

SS

100(nF) V

(V)

T(ms)

I(uA)





(8)

So the default SS time is about 3ms.

If longer SS time is needed, an external SS

capacitor can be added between SS pin and

AGND pin. The external capacitor value can be

determined as follows:

SS

SS

SS

REF

T(ms) I (uA)

C (nF)

100(nF)

V(V)





(9)

Pre-Bias Startup

The MPM3686 has been designed for monotonic

startup into pre-biased loads. If the output is pre-

biased to a certain voltage during startup, the IC

will disable switching for both high-side and low-

side switches until the voltage

on the soft-start capacitor exceeds the sensed

output voltage at the FB pin.

Power Good (PG)

The MPM3686 has a power-good (PG) output.

The PG pin is the open drain of a MOSFET.

Connect it to VCC or some other voltage source

that measures less than 5.5V through a pull-up

resistor (typically 100kΩ). After applying the input

voltage, the MOSFET turns on so that the PG pin

is pulled to GND before the SS is ready. After the

FB voltage reaches 91% of the REF voltage, the

PG pin is pulled high after a 2.5ms delay.

When the FB voltage drops to 80% of the REF

voltage or exceeds 120% of the nominal REF

voltage, the PG pin is pulled low.

If the input supply fails to power the MPM3686,

the PG pin is also pulled low even though this pin

is tied to an external DC source through a pull-up

resistor.

Over-Current Protection (OCP)

The MPM3686 features two current limit levels

for over-current conditions: low-side valley

current limit and low-side negative current limit.

Low-Side

Valley

Current

Limit

: The device

monitors the inductor current during the LS-FET

ON state. If the LS-FET sourcing current is

higher than the internal positive-valley-current

limit, the HS-FET remains OFF and the LS-FET

remains ON for the next ON time. When the LS-

FET sourcing current drops below the valley

current limit, then the LS-FET turns off and the

HS-FET turns on again.

The MPM3686 enters OCP non-latch protection

mode if the LS-FET sourcing valley current keeps

exceeding the valley current limit for a certain

period of time. During OCP, the device tries to

recover from the over-current fault with hiccup

mode: the chip disables the output power stage,

discharges the soft-start capacitor and then

automatically

retries

soft-start.

The

device

repeats this operation cycle as long as the over-

current condition still exists. When the over-

current condition disappears, the MPM3686

initiates a new SS to rise back to regulation level.