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ICS952302

0957B—10/05/04

CLK_STOP# Timing Diagram

CLK_STOP# is an asychronous input to the clock synthesizer. It is used to turn off the CPU clocks for low power

operation. CLK_STOP# is synchronized by the ICS952302.The minimum that the CPU clock is enabled (CLK_STOP#

high pulse) is 100 CPU clocks. All other clocks will continue to run while the CPU clocks are disabled.The CPU clocks

will always be stopped in a low state and start in such a manner that guarantees the high pulse width is a full pulse.

CPU clock on latency is less than 4 CPU clocks and CPU clock off latency is less than 4 CPU clocks.

Notes:

1. All timing is referenced to the internal CPU clock.

2. CLK_STOP# is an asynchronous input and metastable conditions may exist. This signal is

synchronized to the CPU clocks inside the ICS952302.

3. CLK_STOP# signal.

4. All other clocks continue to run undisturbed.

PCICLK

CPUCLK _F

PCI_STOP# (High)

CLK_STOP#

INTERNAL

CPUCLK