PCD6003 datasheet(35/96 Pages) PHILIPS

35 / 96 page

2001 Apr 17

Philips Semiconductors

Product speciﬁcation

Digital telephone answering machine chip

PCD6003

10.8

The test registers CDTRx, PMTRx and TCTRL

The special function registers CDTR1, CDTR2, PMTR1, PMTR2 and TCTRL can put the DSP or CODECs into various

test modes. In these test modes normal operation is not guaranteed. The output behaviour of P3 can be changed and

the DSP test modes can lead to a higher current consumption and to malfunction of the DSP. Three bits however are

accessible by the user: CDTR2.0, PMTR2.0 and PMTR2.2. See Tables 29 and 30 for detailed description.

Table 29 CDTR2 (98H) bit assignment; reset state 00H

Table 30 PMTR2 (98H) bit assignment; reset state 00H

Notes

1. For minimum current consumption in POTS mode (telephone line supplied operation), two bits of these registers

have to be set (PMTR2.0 = 1, CDTR2.0 = 1).

2. For best noise performance of the Sigma Delta AD, chopping has to be enabled (PMTR2.2 = 1).

10.9

Interface to Timing and Control Block (TICB)

The interface to the TICB consists of the special function registers SPCON, CKCON and RTCON and the signals

microcontroller_CLK_EN, microcontroller_CLK, FS_event, Time_event and RTC_event. The signals are described in

Section 10.1.

10.10 Power and Interrupt Control Register (PCON)

Table 31 Power and Interrupt Control Register (SFR address 87H); reset state 00H

Table 32 Description of PCON bits

76543

reserved

avo_off(1)

76543

reserved

atc_chop_en(2)

reserved

avb_off(1)

76543

spare

ARD

spare

WLE/EW

GF1

GF0

IDL

BIT

SYMBOL

DESCRIPTION

−

Spare, may be used as general purpose bit.

ARD

AUX-RAM Disable. If ARD = 1, then the access of a MOVX instruction to the 512 bytes

of the AUX-RAM is disabled. If ARD = 1, then a MOVX operation can access the lower

512 bytes of the external memory. The upper part of the external memory can always

be accessed independently of the setting of the ARD bit.

−

Spare, may be used as general purpose bit.

WLE/EW

Watchdog Load Enable. This ﬂag must be set by software prior to loading the

Watchdog Timer. The ﬂag is reset when the timer is loaded. See Section 10.10.3

GF1

General Purpose Flag 1.

GF0

General Purpose Flag 0.

1PD

Power-down mode select. Setting this bit activates the Power-down mode; see

Section 10.10.2.

IDL

Idle mode select. Setting this bit activates the Idle mode; see Section 10.10.2.

PCD6003 Datasheet(PDF) 35 Page - NXP Semiconductors

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