PCD6003 datasheet(39/96 Pages) PHILIPS

39 / 96 page

2001 Apr 17

Philips Semiconductors

Product speciﬁcation

Digital telephone answering machine chip

PCD6003

Table 35 I2C-bus bit frequencies in Master mode

Note that any I2C-bus device tolerates a maximum and sometimes a minimum SCL frequency. The correct setting of bits

CR2, CR1 and CR0 using a specific microcontroller clock frequency is therefore important.

10.11.2 STATUS REGISTER (S1STA)

S1STA is an 8-bit read-only register. Its contents may be used as a vector to a service routine. This optimizes the

response time of the software and consequently the I2C-bus.

Table 36 Status Register (SFR address D9H); reset state F8H

10.11.3 DATA SHIFT REGISTER (S1DAT)

S1DAT contains the serial data to be transmitted or data that has just been received. Bit 7 is transmitted or received first.

Table 37 Data Shift Register (SFR address DAH); reset state 00H

10.11.4 ADDRESS REGISTER (S1ADR)

This 8-bit ‘own address register’ may be loaded with the 7-bit address to which the controller will respond when

programmed as a slave receiver/transmitter. The LSB bit GC is used to determine whether the general CALL address is

recognized.

Table 38 Address Register (SFR address DBH); reset state 00H

CR2

CR1

CR0

fmicrocontroller_clk

DIVIDED BY

I2C-BUS BIT FREQUENCY (kHz) at fmicrocontroller_clk

0.9 MHz

3.58 MHz

7.16 MHz

14.32 MHz

21 MHz

358

−−−

179

358

−−

119

239

−−

179

358

−

89.5

179

269

120

7.5

59.7

119

179

160

5.6

44.8

89.5

134

111

−

−−−−−

BIT

SYMBOL

DESCRIPTION

7 to 3

SC[4:0]

contains the status code deﬁned by the I2C protocol

2to0

−

not used, all bits are 0

BIT

SYMBOL

DESCRIPTION

7 to 0

S1DAT[7:0]

I2C-bus serial data

BIT

SYMBOL

DESCRIPTION

7 to 1

SLA[6:0]

own I2C-bus address

0: general CALL address is not recognized

1: general CALL address is recognized

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