PCD6003 datasheet(71/96 Pages) PHILIPS

71 / 96 page

2001 Apr 17

Philips Semiconductors

Product speciﬁcation

Digital telephone answering machine chip

PCD6003

16 EXTERNAL I/O INTERFACES

16.1

External analog interfaces

16.1.1

GENERAL PURPOSE ADC AND DAC

For general use, for instance battery management, parallel

set detection or speaker amplifier volume control, a 2-line

multiplexed 8-bit ADC and an 8-bit DAC are on-chip. The

ADC and the DAC consist of several analog sub-blocks

called AVS and AAD, which are controlled by the digital

block DCA (see Fig.33). Block AVS generates voltages in

a time multiplexed way, and acts as a DAC with the

bandgap voltage VBGP as input voltage. Block AAD

contains a comparator that is part of the successive

approximation ADC formed by a combination of AVS, AAD

and DCA. The analog-to-digital conversion can be

performed on two external input signals: AD0IN and

AD1IN.

The whole circuit is active as long as the chip is in

System-on mode. Both the ADC and the DAC can be

controlled by the microcontroller, the SFR mapped

DCA block allowing the user a flexible interface to analog

peripherals.

16.1.2

GENERAL PURPOSE ADC

The on-chip ADC is a two channel multiplexed 8-bit

converter. The control of this converter is done via two bits

in the microcontroller GPADC SFR. One bit selects the

channel and the other bit is the converter request bit. The

request bit is reset by hardware when the converter has

finished its conversion cycle. The ADC (AAD in Fig.33), is

of the successive approximation type.

An internal register contains the value of the slider position

and is changed after each comparison of Vadc with one of

the two possible analog-to-digital inputs (AD0IN and

AD1IN). After 8 comparisons the conversion is finished

and the contents of the internal register is copied into the

(from setting the Request bit until GPADR ready) is less

than 50 ms. This register can in turn be read by the internal

microcontroller.

16.1.2.1

General Purpose ADC Register (GPADC)

Table 64 General Purpose ADC Register (SFR address C3H); reset state 00H

Table 65 Description of GPADC bits

16.1.2.2

General Purpose ADC Result Register (GPADR)

This register holds the 8-bit result value from the conversion. The conversion range is 0 to 2000 mV (VREF) with 8 mV

resolution.

Table 66 General Purpose ADC Result Register (SFR address C2H); reset state 00H, read only

76543210

−−−−−

AADC

REQCOM

BIT

SYMBOL

DESCRIPTION

7to3

−

These 5 bits are reserved.

AADC

Automatic Analog-to-Digital Conversion. If AADC = 1, then a conversion is

performed every 30 ms, regardless of state of request confirm bit.

1CS

Channel Select. If CS = 0, analog-to-digital conversion input is on pin AD0IN. If CS = 1,

analog-to-digital conversion input is on pin AD1IN. Switching of the analog-to-digital

channel is only allowed when no analog-to-digital conversion currently is in progress.

Otherwise the resulting value will be corrupt.

REQCOM

Request Conﬁrm.

76543210

A/D.7

A/D.6

A/D.5

A/D.4

A/D.3

A/D.2

A/D.1

A/D.0

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