V62SLASH12615-01XE-R datasheet(7/97 Pages) TI1

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DP83848-EP

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SLLSEC6E – SEPTEMBER 2012 – REVISED JUNE 2019

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Pin Configuration and Functions

Table 3-1. Package Pin Assignments (continued)

PIN NUMBER

PIN NAME

PHYAD4(RXD_3)

IOGND

IOVDD33

DAP (Die Attach Pad/Thermal Pad)

Table 3-2. Serial Management Interface

TERMINAL

I/O

DESCRIPTION

NAME

NO.

MDC

MANAGEMENT DATA CLOCK: Synchronous clock to the MDIO management data input/output serial interface

which may be asynchronous to transmit and receive clocks. The maximum clock rate is 25 MHz with no minimum

clock rate.

MDIO

I/O

MANAGEMENT DATA I/O: Bi-directional management instruction/ data signal that may be sourced by the

station management entity or the PHY. This pin requires a 1.5-kΩ pullup resistor.

Table 3-3. MAC Data Interface

TERMINAL

I/O

DESCRIPTION

NAME

NO.

TX_CLK

MII TRANSMIT CLOCK: 25-MHz transmit clock output in 100-Mbps mode or 2.5 MHz in 10-Mbps mode

derived from the 25-MHz reference clock.

Unused in RMII mode. The device uses the X1 reference clock input as the 50-MHz reference for both transmit

and receive.

SNI TRANSMIT CLOCK: 10-MHz transmit clock output in 10-Mb SNI mode. The MAC should source TX_EN

and TXD_0 using this clock.

TX_EN

I, PD

MII TRANSMIT ENABLE: Active high input indicates the presence of valid data inputs on TXD[3:0].

RMII TRANSMIT ENABLE: Active high input indicates the presence of valid data on TXD[1:0].

SNI TRANSMIT ENABLE: Active high input indicates the presence of valid data on TXD_0.

TXD_0

MII TRANSMIT DATA: Transmit data MII input pins, TXD[3:0], that accept data synchronous to the TX_CLK

(2.5 MHz in 10-Mbps mode or 25 MHz in 100-Mbps mode).

TXD_1

RMII TRANSMIT DATA: Transmit data RMII input pins, TXD[1:0], that accept data synchronous to the 50-MHz

reference clock.

TXD_2

SNI TRANSMIT DATA: Transmit data SNI input pin, TXD_0, that accept data synchronous to the TX_CLK (10

MHz in 10-Mbps SNI mode).

TXD_3

S, I, PD

RX_CLK

MII RECEIVE CLOCK: Provides the 25-MHz recovered receive clocks for 100-Mbps mode and 2.5 MHz for 10-

Mbps mode.

Unused in RMII mode. The device uses the X1 reference clock input as the 50-MHz reference for both transmit

and receive.

SNI RECEIVE CLOCK: Provides the 10-MHz recovered receive clocks for 10-Mbps SNI mode.

RX_DV

S, O, PD

MII RECEIVE DATA VALID: Asserted high to indicate that valid data is present on the corresponding RXD[3:0].

MII mode by default with internal pulldown.

RMII Synchronous Receive Data Valid: This signal provides the RMII Receive Data Valid indication

independent of Carrier Sense.

This pin is not used in SNI mode.

RX_ER

S, O, PU

MII RECEIVE ERROR: Asserted high synchronously to RX_CLK to indicate that an invalid symbol has been

detected within a received packet in 100-Mbps mode.

RMII RECEIVE ERROR: Assert high synchronously to X1 whenever it detects a media error and RXDV is

asserted in 100-Mbps mode.

This pin is not required to be used by a MAC, in either MII or RMII mode, since the Phy is required to corrupt

data on a receive error.

This pin is not used in SNI mode.

RXD_0

S, O, PD

MII RECEIVE DATA: Nibble-wide receive data signals driven synchronously to the RX_CLK (25 MHz for 100-

Mbps mode, 2.5 MHz for 10-Mbps mode). RXD[3:0] signals contain valid data when RX_DV is asserted.

RXD_1

RMII RECEIVE DATA: 2-bits receive data signals, RXD[1:0], driven synchronously to the X1 clock, 50 MHz.

RXD_2

SNI RECEIVE DATA: Receive data signal, RXD_0, driven synchronously to the RX_CLK. RXD_0 contains

valid data when CRS is asserted. RXD[3:1] are not used in this mode.

RXD_3

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