AD9166 datasheet(4/138 Pages) AD

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AD9166

Data Sheet

Rev. 0 | Page 4 of 138

SPECIFICATIONS

DC SPECIFICATIONS

DAC_2P5_AN = 2.5 V, DAC_1P2_AN = DAC_1P2_CLK = 1.2 V, DAC_N1P2_AN = −1.2 V, DAC_1P2_DIG = 1.2 V, VDD_IO = 2.5 V,

DAC_1P2_SER = 1.2 V, DAC_3P3_SYNC = 3.3 V, AMP_5V_IN = 5.0 V, AMP_3P3_OUT = 3.3 V, AMP_3P3 = 3.3 V, AMP_N5 = −5.0 V,

DAC output full-scale current (IOUTFS) = 40 mA, and TA = −40°C to +85°C, unless otherwise noted. 50 Ω matched output.

Table 1.

Parameter

Test Conditions/Comments

Min

Typ

Max

Unit

RESOLUTION

Bits

DAC ANALOG OUTPUT

Power-Up Delay

From DAC output off to enabled

Gain Error (with Internal Reference)

−1.7

Full-Scale Output Current (

IOUTFS)

Minimum

DAC reference current setting resistor (RSET) = 9.76 kΩ

7.37

8.57

Maximum

RSET = 9.76 kΩ

35.8

38.76

41.3

AMPLIFIER ANALOG OUTPUT

Maximum Full-Scale Power

Measured with full-scale output current set to its typical

maximum

4.3

dBm

9 GHz

FIR85 enabled (2× NRZ)

−9.5

dBm

DEVICE CLOCK INPUT (CLK+, CLK−)

Differential Input Power

Load resistance (RLOAD) = 90 Ω differential on chip

−20

+10

dBm

Common-Mode Voltage

AC-coupled

0.6

Input Impedance1

3 GSPS input clock

Maximum Input Frequency (fCLK)

See

Table 3 for more details

6400

MHz

TEMPERATURE SENSOR

Amplifier Sensor Accuracy2

±5

°C

DAC Sensor Accuracy3

±5

°C

ANALOG SUPPLY VOLTAGES

DAC_2P5_AN

2.375

2.5

2.625

DAC_1P2_AN4

1.14

1.2

1.326

DAC_1P2_CLK4

1.14

1.2

1.326

DAC_N1P2_AN

−1.26

−1.2

−1.14

AMP_5V_IN

4.75

5.25

AMP_3P3_OUT

3.135

3.3

3.465

AMP_N5

−5.25

−5

−4.75

AMP_3P3

3.135

3.3

3.465

DIGITAL SUPPLY VOLTAGES

DAC_1P2_DIG

1.14

1.2

1.326

VDD_IO5

1.71

2.5

3.465

SERDES SUPPLY VOLTAGES

DAC_1P2_SER

1.14

1.2

1.326

DAC_3P3_SYNC

3.135

3.3

3.465

1 See the Clock Input section for more details.

2 The temperature sensor of the amplifier is a more accurate representation of TJ, but requires one-point calibration.

3 Do not use the DAC temperature sensor reading to monitor TJ. Use as a reference only.

4 For the lowest noise performance, use a separate power supply filter network for the DAC_1P2_CLK and the DAC_1P2_AN pins.

5 VDD_IO can range from 1.8 V to 3.3 V, with ±5% tolerance.

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