AD9166 datasheet(16/138 Pages) AD

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AD9166

Data Sheet

Rev. 0 | Page 16 of 138

Pin No.

Mnemonic

Description

B13

AMP_VBG

Amplifier Band Gap Voltage. Connect Pin B13 to a 0.1 μF

capacitor to ground, and a 1 kΩ resistor in series with a

1 μF capacitor to ground. For information about the

voltage measured at this pin, VBGA, see the Amplifier

Junction Temperature Sensor section.

B14

CS_AMP

Amplifier Serial Port Chip Select (Active Low) Input.

CMOS levels on Pin B14 are determined with respect to

VDD_IO.

C3, C4, D3 to D5, D17, E3 to E5, E15 to E17

DAC_N1P2_AN

−1.2 V Analog Supply Voltage.

C5 to C7, C13, C14, D12, D13, D16, G10 to G16, H11,

H13, J9

DAC_2P5_AN

2.5 V Analog Supply Voltage.

C11, D11

AMP_1P8_BYPASS

Bypass Node for Internal1.8 V Analog Supply. Short

Pin C11 and Pin D11 and connect a 1 μF capacitor to

ground.

C16

ISET

DAC Reference Current. Connect Pin C16 with a 9.76 kΩ

resistor (RSET) to DAC_N1P2_AN.

C17

VREF

DAC 1.2 V Reference Input/Output. Connect Pin C17 with

a 1 μF capacitor to ground.

D6, E6

AMP_3P3

3.3 V Analog Supply Voltage.

D7, D8, E9, E10, E11

AMP_N5

−5 V Analog Supply Voltage.

D14, D15

DAC_1P2_AN

1.2 V Analog Supply Voltage.

E1, F1

CLK+, CLK−

Positive and Negative Device Clock Inputs. When FIR85 is

disabled, the input frequency to these pins (fCLK) is the

DAC clock frequency (fDAC). When FIR85 is enabled, fDAC =

2× fCLK.

E7, E8

AMP_3P3_OUT

3.3 V Analog Supply Voltage for the Output Stage of the

Amplifier.

E12, M7, M12

VDD_IO

Supply Voltage for CMOS Input/Output and SPI.

Operational for 1.8 V to 3.3 V plus tolerance (see Table 1

for details).

E13, E14, F5, F6, F12 to F16

DAC_1P2_CLK

1.2 V Clock Supply Voltage.

F7, F8, F9

AMP_5V_IN

5 V Analog Supply Voltage for the Input Stage of the

Amplifier. Pin F7 to Pin F9 internally supply the full-scale

current to the output stage of the DAC.

H1, J1

SYSREF+, SYSREF−

System Reference Positive and Negative Inputs. The H1

and J1 pins are self biased for ac coupling. They both can

be either ac-coupled or dc-coupled.

H7, J8, K13, P8

DNC

Do Not Connect. Do not connect these pins. Leave the

DNC pins floating.

H12

DAC_VBGNEG

DAC Band Gap Voltage. Connect Pin H12 with a 0.1 μF

capacitor to DAC_N1P2_AN.

J12

SDIO

Serial Port Data Input/Output. CMOS levels on Pin J12 are

determined with respect to VDD_IO. See the Serial Data

I/O (SDIO) section for details.

J13

SDO

Serial Port Data Output. CMOS levels on Pin J13 are

determined with respect to VDD_IO.

J14

SCLK

Serial Port Data Clock. CMOS levels on Pin J14 are

determined with respect to VDD_IO. See the Serial Clock

(SCLK) section for details.

L1, M1

SERDIN7+, SERDIN7−

SERDES Lane 7 Negative and Positive Inputs.

L4, L15, M4, M8, M10, M11, M15, N4, N15, P5, P6, P10,

P13, P14, R5 to R7, R13 to R15

DAC_1P2_SER

1.2 V SERDES Digital Supply.

IRQ

Interrupt Request Output (Active Low, Open Drain).

L18, M18

SERDIN0+, SERDIN0−

SERDES Lane 1 Positive and Negative Inputs.

TX_ENABLE

Transmit Enable Input. Pin M5 can be used instead of the

DAC output bias power-down bits in Register 0x040,

Bits[1:0], to enable the DAC output. CMOS levels are

determined with respect to VDD_IO.

AD9166 Datasheet(PDF) 16 Page - Analog Devices

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