AD9166 datasheet(13/138 Pages) AD

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Data Sheet

AD9166

Rev. 0 | Page 13 of 138

SYSREF±

DAC_2P5_AN = 2.5 V, DAC_1P2_AN = DAC_1P2_CLK = 1.2 V, DAC_N1P2_AN = −1.2 V, DAC_1P2_DIG = 1.2 V, VDD_IO = 2.5 V,

DAC_1P2_SER = 1.2 V, DAC_3P3_SYNC = 3.3 V, AMP_5V_IN = 5.0 V, AMP_3P3_OUT = 3.3 V, AMP_3P3 = 3.3 V, AMP_N5 = −5.0 V,

IOUTFS = 40 mA, TA = −40°C to +85°C, unless otherwise noted.

Table 10.

Parameter

Test Conditions/Comments

Min

Typ

Max1

Unit

SYSREF±2

Differential Swing = 1.0 V

Minimum Setup Time, tSYSS

AC-coupled

DC-coupled, common-mode voltage = 0 V

DC-coupled, common-mode voltage = 1.25 V

Minimum Hold Time, tSYSH

AC-coupled

DC-coupled, common-mode voltage = 0 V

DC-coupled, common-mode voltage = 1.25 V

1 The maximum setup and hold times can be inferred from the data sheet for the 11 mm × 11 mm variant of the AD9164, under the assumption that the variations due

to difference in device laminate between the AD9166 and the AD9164 are minimal.

2 The SYSREF± pulse must have a duration longer than the device sample and hold time, plus four additional device clock cycles. For more information, refer to the

SYSREF± Signal section.

SYSREF+

tSYSS

CLK+

tSYSH

MIN 4 CLOCK EDGES

Figure 2. SYSREF± to Device Clock Timing Diagram (Only SYSREF+ and CLK+ Shown)

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