AD9166 datasheet(40/138 Pages) AD

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AD9166

Data Sheet

Rev. 0 | Page 40 of 138

Link Delay Setup Example, with Known Delays

All the known system delays can be used to calculate LMFCVar

and LMFCDel. The example shown in Figure 61 is demonstrated

in the following steps.

Note that this example is in Subclass 1 to achieve deterministic

latency, which has a PCLK factor (4/F) of two frame clock

cycles per PCLK cycle, and uses K = 32 (frames/multiframe).

Because PCBFixed << PCLK Period, PCBFixed is negligible in

this example and not included in the calculations.

Find the receiver delays using Table 6.

RxFixed = 12 PCLK cycles

RxVar = 2 PCLK cycles

Find the transmitter delays. The equivalent table in the

example JESD204B core (implemented on a GTH or

gigabit transceiver (GTX) on a Virtex-6 FPGA) states that

the delay is 56 ± 2 byte clock cycles.

Because the PCLK Rate = ByteRate/4 as described in the

Clock Relationships section, the transmitter delays in

PCLK cycles are calculated as follows:

TxFixed = 54/4 = 13.5 PCLK cycles

TxVar = 4/4 = 1 PCLK cycle

Calculate MinDelayLane as follows:

MinDelayLane = floor(RxFixed + TxFixed + PCBFixed)

= floor(12 + 13.5 + 0)

= floor(25.5)

MinDelayLane = 25

Calculate MaxDelayLane as follows:

MaxDelayLane = ceiling(RxFixed + RxVar + TxFixed +

TxVar + PCBFixed))

= ceiling(12 + 2 + 13.5 + 1 + 0)

= ceiling(28.5)

MaxDelayLane = 29

Calculate LMFCVar as follows:

LMFCVar = (MaxDelay + 1) − (MinDelay − 1)

= (29 + 1) − (25 − 1) = 30 − 24

LMFCVar = 6 PCLK cycles

Calculate LMFCDel as follows:

LMFCDel = (MinDelay − 1) % (K/PClockFactor)

= ((30 − 1)) % (32/2)

= 29 % 16

LMFCDel = 13 PCLK cycles

Write LMFCDel to Register 0x304 for all devices in the

system. Write LMFCVar to Register 0x306 for all devices in

the system.

FRAME CLOCK

LMFC

PCLK

DATA

DATA AT Tx FRAMER

ILAS

LMFCRX

TOTAL FIXED LATENCY = 30 PCLK CYCLES

LMFC DELAY = 26 FRAME CLOCK CYCLES

PCB FIXED

DELAY

DATA

ALIGNED LANE DATA

AT Rx DEFRAMER OUTPUT

ILAS

TOTAL VARIABLE

LATENCY = 4

PCLK CYCLES

Tx VAR

DELAY

Rx VAR

DELAY

Figure 61. LMFC Delay Calculation Example

AD9166 Datasheet(PDF) 40 Page - Analog Devices

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