AD9166 datasheet(39/138 Pages) AD

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Data Sheet

AD9166

Rev. 0 | Page 39 of 138

For proper functioning, all lanes on a link must be read during

the same LMFC period. Section 6.1 of the JESD204B specifica-

tion states that the LMFC period must be larger than the maximum

link delay. For the AD9166, this is not necessarily the case.

Instead, the AD9166 uses a local LMFC for each link (LMFCRx)

that can be delayed from the SYSREF± aligned LMFC.

Because the LMFC is periodic, this delay can account for any

amount of fixed delay. As a result, the LMFC period must only

be larger than the variation in the link delays, and the AD9166 can

achieve proper performance with a smaller total latency.

Figure 59 and Figure 60 show a case where the link delay is

greater than an LMFC period. Note that it can be accommodated

by delaying LMFCRx.

ILAS

DATA

POWER CYCLE

VARIANCE

LMFC

ALIGNED DATA

EARLY ARRIVING

LMFC REFERENCE

LATE ARRIVING

LMFC REFERENCE

Figure 59. Link Delay > LMFC Period Example

The method to select the LMFCDel (Register 0x304), and

LMFCVar (Register 0x306) variables is described in the Link

Delay Setup Example, with Known Delays section.

Setting LMFCDel appropriately ensures that all the corresponding

data samples arrive in the same LMFC period. Then, LMFCVar

is written into the receive buffer delay to absorb all link delay

variation. This write ensures that all data samples have arrived

before reading. By setting these to fixed values across runs and

devices, deterministic latency is achieved.

The receive buffer delay described in the JESD204B specification

takes values from one frame clock cycle to K frame clock cycles,

and the receive buffer delay of the AD9166 takes values from 0

PCLK cycles to 10 PCLK cycles. As a result, up to 10 PCLK

cycles of total delay variation can be absorbed. LMFCVar and

LMFCDel are both in PCLK cycles. The PCLK factor, or

number of frame clock cycles per PCLK cycle, is equal to 4/F.

For more information on this relationship, see the Clock

Relationships section.

Two examples follow that show how to determine LMFCVar

and LMFCDel. After they are calculated, write LMFCDel into

to Register 0x306 for all devices in the system.

ILAS

DATA

FRAME CLOCK

POWER CYCLE

VARIANCE

LMFC

ALIGNED DATA

LMFCRX

LMFC_DELAY_0

LMFC REFERENCE FOR ALL POWER CYCLES

Figure 60. LMFC_DELAY_0 to Compensate for Link Delay > LMFC Period

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