AD9361S-CSL datasheet(5/33 Pages) AD

5 / 33 page

Commercial Space Product

AD9361S-CSL

Rev. 0 | Page 5 of 33

Parameter1

Symbol

Min

Typ

Max

Unit

Test Conditions/

Comments

TRANSMITTERS, 5.5 GHz

Output Return Loss

S22

−10

Maximum Output Power

6.5

dBm

7 MHz tone into 50 Ω

load

Modulation Accuracy (EVM)

−36

40 MHz reference clock

(doubled internally for

RF synthesizer)

Third-Order Output Intermodulation

Intercept Point

OIP3

dBm

Carrier Leakage

−50

dBc

0 dB attenuation

−30

dBc

40 dB attenuation

Noise Floor

−151.5

dBm/Hz

90 MHz offset

Isolation

TX1 to TX2

TX2 to TX1

TX MONITOR INPUTS (TX_MON1,

TX_MON2)

Maximum Input Level

dBm

Dynamic Range

Accuracy

LO SYNTHESIZER

LO Frequency Step

2.4

2.4 GHz, 40 MHz

reference clock

Integrated Phase Noise

800 MHz

0.13

° rms

100 Hz to 100 MHz,

30.72 MHz reference

clock (doubled internally

for RF synthesizer)

2.4 GHz

0.37

° rms

100 Hz to 100 MHz,

40 MHz reference clock

5.5 GHz

0.59

° rms

100 Hz to 100 MHz,

40 MHz reference clock

(doubled internally for

RF synthesizer)

REFERENCE CLOCK

The reference clock is

either the input to the

XTALP/XTALN pins or a

line directly to the

XTALN pin

Input

Frequency Range

MHz

Crystal input

MHz

External oscillator

Signal Level

1.3

V p-p

AC-coupled external

oscillator

AUXILIARY CONVERTERS

ADC

Resolution

Bits

Input Voltage

Minimum

0.05

Maximum

VDDA1P3_BB −

0.05

DAC

Resolution

Bits

Output Voltage

Minimum

0.5

Maximum

VDD_GPO − 0.3

Output Current

AD9361S-CSL Datasheet(PDF) 5 Page - Analog Devices

AD9361S-CSL Datasheet(HTML) 5 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33

Datasheet Download

Link URL