AD9361S-CSL datasheet(6/33 Pages) AD

6 / 33 page

AD9361S-CSL

Commercial Space Product

Rev. 0 | Page 6 of 33

Parameter1

Symbol

Min

Typ

Max

Unit

Test Conditions/

Comments

DIGITAL SPECIFICATIONS (CMOS)

Logic Inputs

Input Voltage

High

VDD_INTERFACE ×

0.8

VDD_INTERFACE

Low

VDD_INTERFACE ×

0.2

Input Current

High

−10

+10

μA

Low

−10

+10

μA

Logic Outputs

Output Voltage

High

VDD_INTERFACE ×

0.8

Low

VDD_INTERFACE ×

0.2

DIGITAL SPECIFICATIONS (LOW

VOLTAGE DIFFERENTIAL SIGNALING

(LVDS)

Logic Inputs

Input Voltage Range

825

1575

Each differential input

in the pair

Input Differential Voltage

Threshold

−100

+100

Receiver Differential Input

Impedance

100

Ω

Logic Outputs

Output Voltage

High

1375

Low

1025

Output Differential Voltage

150

Programmable in 75 mV

steps

Output Offset Voltage

1200

GENERAL-PURPOSE OUTPUTS

Output Voltage

High

VDD_GPO × 0.8

Low

VDD_GPO × 0.2

Output Current

SERIAL PERIPHERAL INTERFACE (SPI)

TIMING

VDD_INTERFACE = 1.8 V

SPI_CLK

Period

tCP

Pulse Width

tMP

SPI_ENB Setup to First SPI_CLK

Rising Edge

tSC

Last SPI_CLK Falling Edge to

SPI_ENB Hold

tHC

SPI_DI

Data Input Setup to SPI_CLK

Data Input Hold to SPI_CLK

SPI_CLK Rising Edge to Output Data

Delay

4-Wire Mode

tCO

3-Wire Mode

tCO

AD9361S-CSL Datasheet(PDF) 6 Page - Analog Devices

AD9361S-CSL Datasheet(HTML) 6 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33

Datasheet Download

Link URL