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AD9361S-CSL Datasheet(PDF) 7 Page - Analog Devices

Part # AD9361S-CSL
Description  RF Agile Transceiver
PDF  33 Pages
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Manufacturer  AD [Analog Devices]
Direct Link  http://www.analog.com
Logo AD - Analog Devices

AD9361S-CSL Datasheet(HTML) 7 Page - Analog Devices

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Commercial Space Product
AD9361S-CSL
Rev. 0 | Page 7 of 33
Parameter1
Symbol
Min
Typ
Max
Unit
Test Conditions/
Comments
Bus Turnaround Time, Read
tHZM
tH
tCO (max)
ns
After baseband
processor (BBP) drives
the last address bit
Bus Turnaround Time, Read
tHZS
0
tCO (max)
ns
After the AD9361S-CSL
drives the last data bit
DIGITAL DATA TIMING (CMOS),
VDD_INTERFACE = 1.8 V
DATA_CLK_x Clock Period
tCP
16.276
ns
61.44 MHz
DATA_CLK_x and FB_CLK_x Pulse
Width
tMP
45% of tCP
55% of tCP
ns
TX Data
TX_FRAME_x, P0_Dx,
and P1_Dx
Setup to FB_CLK_x
tSTX
1
ns
Hold to FB_CLK_x
tHTX
0
ns
DATA_CLK_x to Data Bus Output
Delay
tDDRX
0
1.5
ns
DATA_CLK_x to RX_FRAME_x Delay
tDDDV
0
1.0
ns
Pulse Width
ENABLE
tENPW
tCP
ns
TXNRX
tTXNRXPW
tCP
ns
FDD independent
enable state machine
(ESM) mode
TXNRX Setup to ENABLE
tTXNRXSU
0
ns
Time division duplex
(TDD) ESM mode
Bus Turnaround Time
Before RX
tRPRE
2 × tCP
ns
TDD mode
After RX
tRPST
2 × tCP
ns
TDD mode
Capacitive Load
3
pF
Capacitive Input
3
pF
DIGITAL DATA TIMING (CMOS),
VDD_INTERFACE = 2.5 V
DATA_CLK_x Clock Period
tCP
16.276
ns
61.44 MHz
DATA_CLK_x and FB_CLK_x Pulse
Width
tMP
45% of tCP
55% of tCP
ns
TX Data
TX_FRAME_x, P0_Dx,
and P1_Dx
Setup to FB_CLK_x
tSTX
1
ns
Hold to FB_CLK_x
tHTX
0
ns
DATA_CLK_x to Data Bus Output
Delay
tDDRX
0
1.2
ns
DATA_CLK_x to RX_FRAME_x Delay
tDDDV
0
1.0
ns
Pulse Width
ENABLE
tENPW
tCP
ns
TXNRX
tTXNRXPW
tCP
ns
FDD independent ESM
mode
TXNRX Setup to ENABLE
tTXNRXSU
0
ns
TDD ESM mode
Bus Turnaround Time
Before RX
tRPRE
2 × tCP
ns
TDD mode
After RX
tRPST
2 × tCP
ns
TDD mode
Capacitive Load
3
pF
Capacitive Input
3
pF



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