AD9361S-CSL datasheet(9/33 Pages) AD

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Commercial Space Product

AD9361S-CSL

Rev. 0 | Page 9 of 33

CURRENT CONSUMPTION—VDD_INTERFACE

TX is transmit, and RX is receive.

Table 2. VDD_INTERFACE = 1.2 V

Parameter

Min

Typ

Max

Unit

Test Conditions/Comments

SLEEP MODE

µA

Power applied, device disabled

ONE RX CHANNEL, ONE TX CHANNEL, DOUBLE DATA

RATE (DDR)

Long-Term Evolution (LTE 10 MHz)

Single Port

2.9

30.72 MHz data clock, CMOS

Dual Port

2.7

15.36 MHz data clock, CMOS

LTE 20 MHz

Dual Port

5.2

30.72 MHz data clock, CMOS

TWO RX CHANNELS, TWO TX CHANNELS, DDR

LTE 3 MHz

Dual Port

1.3

7.68 MHz data clock, CMOS

LTE 10 MHz

Single Port

4.6

61.44 MHz data clock, CMOS

Dual Port

5.0

30.72 MHz data clock, CMOS

LTE 20 MHz

Dual Port

8.2

61.44 MHz data clock, CMOS

Global System for Mobile Communications (GSM)

Dual Port

0.2

1.08 MHz data clock, CMOS

Table 3. VDD_INTERFACE = 1.8 V

Parameter

Min

Typ

Max

Unit

Test Conditions/Comments

SLEEP MODE

μA

Power applied, device disabled

ONE RX CHANNEL, ONE TX CHANNEL, DDR

LTE 10 MHz

Single Port

4.5

30.72 MHz data clock, CMOS

Dual Port

4.1

15.36 MHz data clock, CMOS

LTE 20 MHz

Dual Port

8.0

30.72 MHz data clock, CMOS

TWO RX CHANNELS, TWO TX CHANNELS, DDR

LTE 3 MHz

Dual Port

2.0

7.68 MHz data clock, CMOS

LTE 10 MHz

Single Port

8.0

61.44 MHz data clock, CMOS

Dual Port

7.5

30.72 MHz data clock, CMOS

LTE 20 MHz

Dual Port

14.0

61.44 MHz data clock, CMOS

GSM

Dual Port

0.3

1.08 MHz data clock, CMOS

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