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M69KB096AB Datasheet(PDF) 35 Page - STMicroelectronics |
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M69KB096AB Datasheet(HTML) 35 Page - STMicroelectronics |
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35 / 73 page  M69KB096AB 7 Configuration Registers 35/73 Table 11. Refresh Configuration Register Definition Address Bits Refresh Configuration Register Bits Name Value Description A15-A8 - - Must be set to ‘0’ Reserved A7 RCR7 Page Mode Operation Bit 0 Page Read Mode Disabled (Default) 1 Page Read Mode Enabled A6-A5 - - Must be set to ‘0’ Reserved A4 RCR4 Deep Power- Down Bit 0 Deep Power-Down Enabled 1 Deep Power-Down Disabled (Default) A3 - - Must be set to ‘0’ Reserved A2-A0 RCR2-RCR0 Partial Array Refresh Bits 000 Full Array Refresh (Default) 001 Refresh of the Bottom Half of the Array 010 Refresh of the Bottom Quarter of the Array 011 Refresh of the Bottom Eighth of the Array 100 None of the Array 101 Refresh of the Top Half of the Array 110 Refresh of the Top Quarter of the Array 111 Refresh of the Top Eighth of the Array |
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