HC705RC16GRSSLASHD datasheet(21/120 Pages) NXP

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General Description

Signal Description

MC68HC705RC16 — Rev. 3.0

General Release Specification

General Description

The MCU completes the current instruction before it responds to the

interrupt request. When IRQ goes low for at least one t

ILIH (see 12.8

Control Timing (5.0 Vdc and 3.3 Vdc)), a logic 1 is latched internally to

signify that an interrupt has been requested. When the MCU completes

its current instruction, the interrupt latch is tested. If the interrupt latch

contains a logic 1 and the interrupt mask bit (I bit) in the condition code

If the option is selected to include level-sensitive triggering, the IRQ input

requires an external resistor to V

DD for wired-OR operation.

The IRQ pin contains an internal Schmitt trigger as part of its input to

improve noise immunity.

Refer to 4.2 Introduction for more detail.

1.5.3 OSC1 and OSC2

These pins provide control input for an on-chip clock oscillator circuit. A

crystal, a ceramic resonator, or an external signal connects to these pins

to provide a system clock. The oscillator frequency is two times the

internal bus rate.

Figure 1-5 shows the recommended circuit when using a crystal. The

crystal and components should be mounted as close as possible to the

input pins to minimize output distortion and startup stabilization time.

A ceramic resonator may be used in place of the crystal in cost-sensitive

applications. Figure 1-5 (a) shows the recommended circuit for using a

ceramic resonator. The manufacturer of the particular ceramic resonator

being considered should be consulted for specific information.

An external clock should be applied to the OSC1 input with the OSC2 pin

not connected (see Figure 1-5 (b)). This setup can be used if the user

does not want to run the CPU with a crystal.

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

HC705RC16GRS/D Datasheet(PDF) 21 Page - NXP Semiconductors