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HC705RC16GRS/D Datasheet(PDF) 39 Page - NXP Semiconductors |
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HC705RC16GRS/D Datasheet(HTML) 39 Page - NXP Semiconductors |
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39 / 120 page  Interrupts Hardware Interrupts MC68HC705RC16 — Rev. 3.0 General Release Specification Interrupts 4.6 Hardware Interrupts All hardware interrupts except RESET are maskable by the I bit in the CCR. If the I bit is set, all hardware interrupts (internal and external) are disabled. Clearing the I bit enables the hardware interrupts. The three types of hardware interrupts are explained in the following sections. 4.7 External Interrupt (IRQ/Port B Pullup) The IRQ pin provides an asynchronous interrupt to the CPU. A block diagram of the IRQ function is shown in Figure 4-2. NOTE: The BIH and BIL instructions will apply to the level on the IRQ pin itself and to the output of the logic OR function with the port B IRQ interrupts. The states of the individual port B pins can be checked by reading the appropriate port B pins as inputs. The IRQ pin is one source of an external interrupt. All port B pins (PB0–PB7) act as other external interrupt sources if the pullup feature is enabled as specified by the user. Figure 4-2. IRQ Function Block Diagram IRQ LATCH R IRQ PIN LEVEL (MASK OPTION) TO IRQ PROCESSING IN CPU PORT B KEYSCAN INTERRUPT TO BIH & BIL INSTRUCTION SENSING RST IRQ VECTOR FETCH VDD EIMSK Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com |
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