56F8167 datasheet(28/184 Pages) FREESCALE

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56F8367 Technical Data, Rev. 8

Freescale Semiconductor

Preliminary

TXD1

(GPIOD6)

Output

Input/

Output

In reset,

output is

disabled,

pull-up is

enabled

Transmit Data — SCI1 transmit data output

Port D GPIO — This GPIO pin can be individually programmed

as an input or output pin.

After reset, the default state is SCI output.

To deactivate the internal pull-up resistor, clear bit 6 in the

GPIOD_PUR register.

RXD1

(GPIOD7)

Input

Input/

Output

Input,

pull-up

enabled

Receive Data — SCI1 receive data input

Port D GPIO — This GPIO pin can be individually programmed

as an input or output pin.

After reset, the default state is SCI input.

To deactivate the internal pull-up resistor, clear bit 7 in the

GPIOD_PUR register.

TCK

137

Schmitt

Input

Input,

pulled low

internally

Test Clock Input — This input pin provides a gated clock to

synchronize the test logic and shift serial data to the

JTAG/EOnCE port. The pin is connected internally to a pull-down

resistor.

TMS

138

Schmitt

Input

Input,

pulled high

internally

Test Mode Select Input — This input pin is used to sequence the

JTAG TAP controller’s state machine. It is sampled on the rising

edge of TCK and has an on-chip pull-up resistor.

To deactivate the internal pull-up resistor, set the JTAG bit in the

SIM_PUDR register.

Note:

Always tie the TMS pin to VDD through a 2.2K resistor.

TDI

139

Schmitt

Input

Input,

pulled high

internally

Test Data Input — This input pin provides a serial input data

stream to the JTAG/EOnCE port. It is sampled on the rising edge

of TCK and has an on-chip pull-up resistor.

To deactivate the internal pull-up resistor, set the JTAG bit in the

SIM_PUDR register.

TDO

140

Output

In reset,

output is

disabled,

pull-up is

enabled

Test Data Output — This tri-stateable output pin provides a serial

output data stream from the JTAG/EOnCE port. It is driven in the

shift-IR and shift-DR controller states, and changes on the falling

edge of TCK.

Table 2-2 Signal and Package Information for the 160-Pin LQFP and MBGA (Continued)

Signal

Name

No.

Ball No.

Type

State

During

Reset

Signal Description

56F8167 Datasheet(PDF) 28 Page - Freescale Semiconductor, Inc

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