| Electronic Components Datasheet Search |
|
STAC9766 Datasheet(PDF) 21 Page - Integrated Device Technology |
|
|
|||||||||||||||||||||||||||||
STAC9766 Datasheet(HTML) 21 Page - Integrated Device Technology |
|
21 / 97 page ![]() STAC9766/9767 TWO-CHANNEL, 20-BIT, AC’97 2.3 CODECS WITH STEREO MICROPHONE AND MIC/JACK SENSING PC AUDIO IDT™ 21 STAC9766/9767 V 7.4 12/06 TWO-CHANNEL, 20-BIT, AC’97 2.3 CODECS WITH STEREO MICROPHONE AND MIC/JACK SENSING Figure 12. CODEC Clock Source Detection The STAC9766/9767 uses the XTAL_OUT pin (pin 3) and the CID0 and CID1 pins (pins 45 & 46) to determine its alternate clock frequencies. See section 2.2.4: page14 for additional information on Crystal Elimination and for supported clock frequencies. If, when the RESET# signal has been de-asserted, the CODEC has not detected a signal on BIT_CLK, as defined in the previous paragraph, then the AC‘97 CODEC derives its clock internally from an externally attached 24.576 MHz crystal or oscillator (or optionally from an external 14.318 MHz oscillator), and drives a buffered 12.288 MHz clock to its digital companion Controller over AC-link under the signal name “BIT_CLK”. Clock jitter at the DACs and ADCs is a fundamental impediment to high quality output, and the internally generated clock will provide AC‘97 with a clean clock that is independent of the physical proximity of AC‘97’s companion Digital Controller (hence- forth referred to as “the Controller”). If BIT_CLK begins toggling while the RESET# signal is still asserted, the clock is being provided by other than the primary CODEC, for instance by the controller or by a discrete clock source. In this case, the primary CODEC must act as a consumer of the BIT_CLK signal as if it were a secondary CODEC. AC'97 Clock Source Detection RESET# Signal Asserted BIT_CLK Toggling? 12.288MHz signal on BIT_CLK is being generated externally; codec uses this signal as the clock. Yes No After RESET# Signal Deasserted 24.576MHz crystal present? 24.576MHz Crystal on XTL_IN and XTL_OUT used by codec to generate clock on BIT_CLK Yes 24.576MHz oscillator present? No 24.576 MHz signal on XTL_IN used by codec to generate 12.288MHz clock on BIT_CLK Yes 14.318MHz oscillator presnent? No 14.318 MHz signal on XTL_IN used by codec to generate 12.288MHz clock on BIT_CLK Yes Error condition - no clock source present No |
|
Link URL |
| Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Contact us | Privacy Policy | Link to Datasheet | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |