STAC9766 datasheet(78/97 Pages) IDT

78 / 97 page

STAC9766/9767

TWO-CHANNEL, 20-BIT, AC’97 2.3 CODECS WITH STEREO MICROPHONE AND MIC/JACK SENSING

PC AUDIO

IDT™

STAC9766/9767

V 7.4 12/06

TWO-CHANNEL, 20-BIT, AC’97 2.3 CODECS WITH STEREO MICROPHONE AND MIC/JACK SENSING

8.4.11.

EAPD Access Register (74h)

Default: 0800h

Bit(s) Reset Value

Name

Description

15:8

RESERVED Reserved

INT_APOP

0 = Anti Pop Enabled

1 = Anti Pop Disabled

The STAC9766/9767 includes an internal power supply anti-pop circuit that

prevents audible clicks and pops from being heard when the CODEC is powered

on and off. This function is accomplished by delaying the charge/discharge of the

VREF capacitor (Pin 27). C VREF value of 1 µF will cause a turn-on delay of roughly

3 seconds, which will allow the power supplies to stabilize before the CODEC

outputs are enabled. The delay will be extended to 30 seconds if a CVREF value of

µF is used. The CODEC outputs are also kept stable for the same amount of

time at power-off to allow the system to be gracefully turned off. The INT_APOP bit

allows this delay circuit to be bypassed for rapid production testing. Any external

component anti-pop circuit is unaffected by the internal circuit.

6:0

RESERVED Reserved

D15

D14

D13

D12

D11

D10

EAPD

RESERVED

EAPD_OEN

RESERVED

INTDIS

GPIOACC

GPIOSLT12

Bit(s) Reset Value

Name

Description

EAPD

EAPD data Enable

EAPD data output on EAPD when bit D11 = 1

EAPD data input from pin when bit D11 = 0

14:12

RESERVED Bit not used, should read back 0

EAPD_OEN

EAPD Pin Enable

0 = EAPD configured as input pin

1 = EAPD configured as output pin

10:3

RESERVED Bit not used, should read back 0

INTDIS

Interrupt disable option.

Interrupts cleared by writing a 1 to I4 (Reg24h:D15)

0 = will clear both SENSE and GPIO interrupts

1 = will only clear SENSE interrupts. GPIO interrupts will have to be cleared in

Reg54h.

GPIOACC

GPIO ACCESS

0 = ACLINK access from GPIO Pads

1 = ACLINK access from GPIO Register 54h

GPIOSLT12

0 = GPIO0/1 access via Reg54h when GPIO is set as an output, for input Slot12

data will be 0h.

1 = GPIO0/1 access via Slot 12 when GPIO is set as an output, for inputs

Reg54h will not be updated.

This can only be used if a modem CODEC is not present in the system and using

Slot12.

STAC9766 Datasheet(PDF) 78 Page - Integrated Device Technology

STAC9766 Datasheet(HTML) 78 Page - Integrated Device Technology

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97

Datasheet Download

Link URL