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STAC9766 Datasheet(PDF) 13 Page - Integrated Device Technology |
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STAC9766 Datasheet(HTML) 13 Page - Integrated Device Technology |
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13 / 97 page ![]() STAC9766/9767 TWO-CHANNEL, 20-BIT, AC’97 2.3 CODECS WITH STEREO MICROPHONE AND MIC/JACK SENSING PC AUDIO IDT™ 13 STAC9766/9767 V 7.4 12/06 TWO-CHANNEL, 20-BIT, AC’97 2.3 CODECS WITH STEREO MICROPHONE AND MIC/JACK SENSING 2.2. AC Timing Characteristics (Tambient = 25 °C, AVdd = 3.3 V or 5 V ± 5%, DVdd = 3.3V ± 5%, AVss = DVss = 0 V; 75pF external load for BIT_CLK and 60pF external load for SDATA_IN) 2.2.1. Cold Reset Figure 2. Cold Reset Timing Note: BIT_CLK and SDATA_IN are in a high impedance state during reset. 2.2.2. Warm Reset Figure 3. Warm Reset Timing Parameter Symbol Min Typ Max Units RESET# active low pulse width Tres_low 1.0 - - µs RESET# inactive to SDATA_IN or BIT_CLK active delay Tri2actv - - 25 ns RESET# inactive to BIT_CLK startup delay Trst2clk 0.01628 - 400 µs BIT_CLK active to RESET# asserted (Not shown in diagram) Tclk2rst 0.416 - - µs Parameter Symbol Min Typ Max Units SYNC active high pulse width Tsync_high 1.0 1.3 - µs SYNC inactive to BIT_CLK startup delay Tsync2clk 162.8 - - ns Tres_low Trst2clk RESET# BIT_CLK SDATA_IN Ttri2actv Ttri2actv Tsync_high Tsync_2clk SYNC BIT_CLK |
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