TMP86CS64AFG datasheet(41/202 Pages) TOSHIBA

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Page 31

TMP86CS64AFG

• Entering IDLE0 or SLEEP0 mode

Disable on-chip peripherals such as a timer counter. To enter the IDLE0 or SLEEP0 mode,

set SYSCR2<TGHALT> to 1.

• Exiting IDLE0 or SLEEP0 Mode

Upon return from the IDEL0 or SLEEP0 mode, the interrupt master enable flag (IMF) deter-

mines the action taken after exiting the IDEL0 or SLEEP0 mode; i.e., whether execution

resumes with an interrupt service routine. When exiting the IDEL0 or SLEEP0 mode,

SYSCR2<TGHALT> is automatically cleared to 0, and the operating mode is returned to the

mode before entering the IDEL0 or SLEEP0 mode. When TBTCR<TBTEN> is set to 1 at this

time. the INTTBT interrupt latch is set.

The IDLE0 or SLEEP0 mode is exited by setting the RESET pin to low. In this case,

the NORMAL1 mode is activated after exiting the IDLE1/2 or SLEEP1/2.

Note: The IDLE0 or SLEEP0 mode is entered and exited regardless of TBTCR<TBTEN> setting.

(1) Program execution resuming with the instruction (IMF, EF8, TBTCR<TBTEN> = 0)

When detecting the falling edge of the source clock set in TBTCR<TBTCK>, the IDLE0 or

SLEEP0 mode is exited. When the IDLE0 or SLEEP0 mode is exited, program execution resumes

with the instruction immediately following the instruction that activated the IDLE0 or SLEEP0

mode. When TBTCR<TBTEN> is set to 1, the time base timer interrupt latch is set.

(2) Program execution resuming with the interrupt service routine (IMF, EF8,

TBTCR<TBTEN> = 1)

When detecting the falling edge of the source clock set in TBTCR<TBTCK>, the IDLE0 or

SLEEP0 mode is exited, and then INTTBT interrupt processing is performed.

Note 1: The IDLE0 or SLEEP0 mode is returned to the NORMAL1 or SLEEP1 mode by the asynchro-

nous internal clock specified in TBTCR<TBTCK>, the period time of IDLE0 or SLEEP0 mode is

shorter than the period set in TBTCR<TBTCK>.

Note 2: When a watchdog timer interrupt is generated immediately before entering the IDLE1/2 or

SLEEP1/2 mode, the watchdog timer interrupt is processed, without entering the IDLE1/2 or

SLEEP1/2 mode.

Note 3: When IL8ER in interrupt source selector (INTSEL) is set to "1", the program execution resumes

with the instruction immediately following the instruction that activated the IDLE0 or SLEEP0

mode even though all of IMF, EF8 and TBTCR<TBTEN> are set to "1".

TMP86CS64AFG Datasheet(PDF) 41 Page - Toshiba Semiconductor