TMP86CS64AFG datasheet(28/202 Pages) TOSHIBA

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Page 18

2. Operational Descriptions

2.2 System Clock Controller

TMP86CS64AFG

(2) SLOW2 Mode

The CPU core operates with low-frequency clock. Switching from NORMAL2 to SLOW2, and

vise-versa is programmed in SYSCR2<SYSCK>. Do not clear XTEN to 0 in the SLOW2 mode.

(3) SLOW1 Mode

Power dissipation can be reduced by stopping high-frequency clock oscillation, and operating the

CPU core and on-chip peripherals with low-frequency clock.

Switching from SLOW1 to SLOW2, and vise-versa is programmed in SYSCR2<XEN>. In the

SLOW1 and SLEEP1 modes, output from the 1st to 6th stages is stopped.

(4) IDLE2 Mode

The CPU and watchdog timer are halted, and on-chip peripherals are operated with the high- and

low-frequency clocks. Entering and exiting the IDLE2 mode is the same as for the IDLE1 mode.

After exiting the IDLE2 mode, the CPU returns to the NORMAL2 mode.

(5) SLEEP1 Mode

The CPU and watchdog timer are halted, and on-chip peripherals are operated with the low-fre-

quency clock. Entering and exiting the SLEEP1 mode is the same as for the IDLE1 mode. After exit-

ing the SLEEP1 mode, th CPU returns to the SLOW1 mode. High-frequency clock oscillation is

stopped. In the SLOW1 and SLEEP1 modes, output from the 1st to 6th stages is stopped.

(6) SLEEP2 Mode

The SLEEP2 mode is the idle mode corresponding to the SLOW2 mode. The SLEEP2 mode is the

same as the SLOW2 mode except that high-frequency clock is activated.

(7) SLEEP0 Mode

The CPU and on-chip peripherals are halted except oscillator and TBT. The SLEEP0 mode is

entered by setting the system control register SYSCR2<TGHALT> to 1 in the SLOW1 mode. When

the SLEEP0 mode is entered, the CPU is halted and the timing generator stops clocking to the

peripherals except TBT. When detecting the falling edge of the source clock set in

TBTCR<TBTCK>, the timing generator starts the clocking operation to all on-chip peripherals.

When the SLEEP0 mode is exited, the CPU restarts operation and returns to the SLOW1 mode. the

CPU enters to the SLEEP0 mode and returns to the SLOW1 mode regardless of setting in

TBTCR<TBTEN>. Interrupt processing is performed when IMF = 1, EF8 (TBT interrupt enable

flag) = 1, and TBTCR<TBTEN> = 1.

When the SLEEP0 mode is entered with TBTCR<TBTEN> = 1, INTTBT interrupt latch is set

after returning to the SLOW1 mode.

TMP86CS64AFG Datasheet(PDF) 28 Page - Toshiba Semiconductor