TMP86CS64AFG datasheet(51/202 Pages) TOSHIBA

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TMP86CS64AFG

3.2.2 Individual interrupt enable flags (EF15 to EF4)

Each of these flags enables and disables the acceptance of its maskable interrupt. Setting the corresponding

bit of an individual interrupt enable flag to “1” enables acceptance of its interrupt, and setting the bit to “0” dis-

ables acceptance. During reset, all the individual interrupt enable flags (EF15 to EF4) are initialized to “0” and

all maskable interrupts are not accepted until they are set to “1”.

Note:In main program, before manipulating the interrupt enable flag (EF) or the interrupt latch (IL), be sure to clear

IMF to "0" (Disable interrupt by DI instruction). Then set IMF newly again as required after operating on the EF

or IL (Enable interrupt by EI instruction)

In interrupt service routine, because the IMF becomes "0" automatically, clearing IMF need not execute nor-

mally on interrupt service routine. However, if using multiple interrupt on interrupt service routine, manipulat-

ing EF or IL should be executed before setting IMF="1".

Example 1 :Enables interrupts individually and sets IMF

; IMF

← 0

LDW

(EIRL), 1110100010100000B

; EF15 to EF13, EF11, EF7, EF5

← 1

Note: IMF should not be set.

; IMF

← 1

Example 2 :C compiler description example

unsigned int _io (3AH) EIRL;

/* 3AH shows EIRL address */

_DI();

EIRL = 10100000B;

_EI();

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