TMP86CS64AFG datasheet(32/202 Pages) TOSHIBA

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Page 22

2. Operational Descriptions

2.2 System Clock Controller

TMP86CS64AFG

Note 1: Reset is performed when both XEN and XTEN are cleared to 0, XEN is cleared to 0 with SYSCK = 0, or XTEN is cleared

to 0 with SYSCK = 1.

Note 2: WDT: watchdog timer, TG: timing generator, *: Don’t care

Note 3: When the bit 3, 1 or 0 of SYSCR2 is read, a don't care is read.

Note 4: Do not set IDLE and TGHALT to 1 simultaneously.

Note 5: Since the IDLE0/SLEEP0 mode is returned to the NORMAL1/SLOW1 mode by the asynchronous internal source clock

specified in TBTCR<TBTCK>, the time to return to the NORMAL1/SLOW1 mode from the IDLE0/SLEEP0 mode is shorter

than the period time specified in TBTCR<TBTCK>.

Note 6: Upon exit from the IDLE1/2 or SLEEP1/2 mode, IDLE is automatically cleared to 0.

Note 7: Upon exit from the IDLE0 or SLEEP0 mode, TGHALT is automatically cleared to 0.

Note 8: When setting TGHAL to 1, stop functions of on-chip peripherals beforehand. If not stopped, an interrupt latch to the

peripherals may be set immediately after the IDLE0 or SLEEP0 mode is exited.

System Control Register 2

3210

SYSCR2

(0039H)

XEN

XTEN

SYSCK

IDLE

TGHAL

(Initial value: 1000 *0**)

XEN

High-frequency oscillator control

0: Stop oscillation

1: Continue or start oscillation

R/W

XTEN

Low-frequency oscillator control

0: Stop oscillation

1: Continue or start oscillation

SYSCK

System clock select (write)/monitor

(read)

0: High-frequency clock (NORMAL1/NORMAL2/IDLE1/IDLE2)

1: Low-frequency clock (SLOW/SLEEP)

IDLE

CPU and WDT control

(IDLE1/2, SLEEP1/2 mode)

0: CPU, WDT enabled

1: CPU, WDT disabled (Enter IDLE1/2, SLEEP1/2 mode)

R/W

TGHALT

TG control

(IDLE0, SLEEP0 mode)

0: Clocking operation to all peripherals from TG

1: Stop the clocking operation to peripherals except TBT from TG

(Enter IDLE0, SLEEP0 mode)

R/W

TMP86CS64AFG Datasheet(PDF) 32 Page - Toshiba Semiconductor

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