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SMC032AF Datasheet(PDF) 40 Page - Numonyx B.V |
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SMC032AF Datasheet(HTML) 40 Page - Numonyx B.V |
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40 / 82 page  Software interface SMCxxxAF 40/82 Accesses to even addresses between 400h and 7FFh access register 8. Accesses to odd addresses between 400h and 7FFh access register 9. This 1 Kbyte memory window to the data register is provided so that hosts can perform memory-to-memory block moves to the data register when the register lies in memory space. Some hosts, such as the X86 processors, must increment both the source and destination addresses when executing the memory-to-memory block move instruction. Some PCMCIA socket adapters also have an embedded auto incrementing address logic. A word access to address at offset 8 will provide even data on the least significant byte of the data bus, along with odd data at offset 9 on the most significant byte of the data bus. Table 36. Memory mapped decoding – REG A10 A9 to A4 A3 A2 A1 A0 Offset – OE=0 – WE=0 1 0 X 0000 0h Even Data register Even Data register 1 0 X 0001 1h Error register Feature register 1 0 X 0010 2h Sector Count register Sector Count register 1 0 X 0011 3h Sector Number register Sector Number register 1 0 X 0100 4h Cylinder Low register Cylinder Low register 1 0 X 0101 5h Cylinder High register Cylinder High register 1 0 X 0110 6h Select Card/Head register Select card/Head register 1 0 X 0111 7h Status register Command register 1 0 X 1000 8h Dup. Even Data register Dup. Even Data register 1 0 X 1001 9h Dup. Odd Data register Dup. Odd Data register 1 0 X 1101 Dh Dup. Error register Dup. Feature register 1 0 X 1110 Eh Alternate Status register Device Control register 1 0 X 1111 Fh Drive Address register Reserved 1 1 X X X X 0 8h Even Data register Even Data register 1 1 X X X X 1 9h Odd Data register Odd Data register |
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