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SMC032AF Datasheet(PDF) 48 Page - Numonyx B.V |
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SMC032AF Datasheet(HTML) 48 Page - Numonyx B.V |
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48 / 82 page  CF-ATA registers SMCxxxAF 48/82 8.9 Status & alternate status registers (address 1F7h [177h] & 3F6h [376h]; offsets 7 & Eh) These registers return the card status when read by the host. Reading the status register clears a pending interrupt. Reading the auxiliary status register does not clear a pending interrupt. The status register should be accessed in Byte mode; in Word mode it is recommended that alternate status register is used. The status bits are described as follows 8.9.1 Bit 7 (BUSY) The busy bit is set when only the card can access the command register and buffer. The host is denied access. No other bits in this register are valid when this bit is set to ‘1’. 8.9.2 Bit 6 (RDY) This bit indicates whether the device is capable of performing CompactFlash memory card operations. This bit is cleared at power-up and remains cleared until the card is ready to accept a command. 8.9.3 Bit 5 (DWF) When set this bit indicates a write fault has occurred. 8.9.4 Bit 4 (DSC) This bit is set when the card is ready. 8.9.5 Bit 3 (DRQ) The data request is set when the card requires information be transferred either to or from the host through the data register. The bit is cleared by the next command. 8.9.6 Bit 2 (CORR) This bit is set when a correctable data error has been encountered and the data has been corrected. This condition does not terminate a multi-sector read operation. 8.9.7 Bit 1 (IDX) This bit is always set to ‘0’. 8.9.8 Bit 0 (ERR) This bit is set when the previous command has ended in some type of error. The bits in the error register contain additional information describing the error. In case of read or write access commands that end with an error, the address of the first sector with an error is in the command block registers. This bit is cleared by the next command. |
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