CSG14K_CSG8K datasheet(80/114 Pages) AMSOSRAM

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CSG14K_CSG8K

Functional Description

Datasheet

• PUBLIC

DS000571

• v2-01 • 2023-Feb-10

113

│ 79

Each of these windows is configured with an YWINi register that defines the position, size and

sub-sampling of the window. The 31 bits of each YWINi register span 4 physical SPI

addresses. In the table below, only the start address is given (the upper address being

21+4×i).

The readout direction of all windows can be changed from the default incrementing addresses

(bottom to top) to decrementing addresses (top to bottom) with the YWIN_DIR register. Using

a different setting for this register on both sides of the readout allows for reading out from

center to edge or vice versa.

Figure 95:

Vertical Windows Registers

Bank

Addr

Bits

Description

YWIN_ENA

28-29

[9:0]

One bit per window

0: Disable

1: Enable

YWIN_BLACK

[9:0]

One bit per window to control the

‘Electrical Black’ mode

0: Disable

1: Enable

YWIN_DIR

[0:0]

Direction of readout addresses

0: Count upwards

1: Count downwards

YWINi.SIZE

18+4×i

[13:0]

Number of read out rows in window i

YWINi.START

18+4×i

[27:14]

Physical address of first row in window i

YWINi.SUBS

18+4×i

[30:28]

Row subsampling in window i

Ratio = 1/(2SUBS)

The START address of a window should comply with the values in Figure 94.

Only windows for which the respective bit in YWIN_ENA is set high are actually read out. This

way multiple relevant Y-window specifications can be stored in the register map at the same

time, enabling only the relevant ones.

All enabled windows are concatenated together (the first row of a new window is read

immediately after the last row of the previous). The number of rows actually read in one frame

(= # of DVAL within one FVAL) is the sum of the SIZE fields of all windows enabled by

YWIN_ENA.

The figure below shows an example of using multiple windows.

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