RZSLASHN2L datasheet(4/128 Pages) RENESAS

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Table 1.6

Event link

Feature

Functional description

Event link controller (ELC)

● Up to 217 event signals can be interlinked with the operation of modules.

● In particular, the operation of timer modules can be started by input event signals.

● Event-linked operation of signals of ports 16 and port 18 is to be possible.

Table 1.7

Timers (1 of 2)

Feature

Functional description

Multi-function timer pulse unit 3 (MTU3)

● 9 channels (16 bits × 8 channels, 32 bits × 1 channel)

● Maximum of 28 pulse-input/output and 3 pulse-input possible

● Select from among 10, 11, 12, or 14 counter-input clock signals for each channel (with

maximum operating frequency of 200 MHz)

● Input capture function

● 39 output compare/input capture registers

● Counter clear operation (synchronous clearing by compare match/input capture)

● Simultaneous writing to multiple timer counters (TCNT)

● Simultaneous register input/output by synchronous counter operation

● Buffered operation

● Support for cascade-connected operation

● Automatic transfer of register data

● Pulse output mode

Toggle/PWM/complementary PWM/reset-synchronized PWM

● Complementary PWM output mode

- Outputs non-overlapping waveforms for controlling 3-phase inverters

- Automatic specification of dead times

- PWM duty cycle: Selectable as any value from 0% to 100%

- Delay can be applied to requests for A/D conversion.

- Non-generation of interrupt requests at peak or trough values of counters can be selected.

- Double buffer configuration

● Reset synchronous PWM mode

Six phases of positive and negative PWM waveforms can be output with desired duty

cycles.

● Phase-counting mode: 16-bit mode (channels 1 and 2), 32-bit mode (channels 1 and 2 in

cascade connection)

● Counter functionality for dead-time compensation

● Generation of triggers for A/D converter conversion

● A/D converter start triggers can be skipped

● Digital noise filter function for signals on the input capture and external counter clock pins

● Event linking by the ELC

General PWM timer (GPT)

● 32 bits × 18 channels

● Counting up or down (saw-wave), counting up and down (triangle-wave) selectable for all

channels

● Select from among four counter-input clock signals for each channel (with maximum

operating frequency of 200 MHz)

● 2 input/output pins per channel

● 2 output compare/input capture registers per channel

● For the 2 output compare/input capture registers of each channel, 4 registers are provided

as buffer registers and are capable of operating as comparison registers when buffering is

not in use.

● In output compare operation, buffer switching can be at peaks or troughs, enabling the

generation of laterally asymmetrically PWM waveforms.

● Registers for setting up frame intervals on each channel (with capability for generating

interrupts on overflow or underflow)

● Synchronizable operation of the several counters

● Modes of synchronized operation (synchronized, or displaced by desired times for phase

shifting)

● Generation of dead times in PWM operation

● Through combination of 3 counters, generation of automatic 3-phase PWM waveforms

incorporating dead times

● Starting, clearing, stopping, switching, up/down counters, and input capture in response to

external or internal triggers

● Starting, clearing, stopping, switching, up/down counters, and input capture in response to

input level comparison

● Internal trigger sources: software and compare-match

● Generation of triggers for A/D converter conversion

● Digital noise filter function for signals on the input capture and external trigger pins

● Event linking by the ELC

RZ/N2L Datasheet

1. Overview

R01DS0397EJ0140 Rev.1.40

Mar 31, 2026

Page 4 of 128

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