RZSLASHN2L datasheet(8/128 Pages) RENESAS

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Table 1.9

Analog

Feature

Functional description

12-bit A/D converter (ADC12)

● 12 bits × 2 units (unit 0: 4 channels, unit 1: 8 channels)

● 12-bit resolution

● Conversion time

0.84 µs per channel

● Operating mode

Scan mode (single scan mode, continuous scan mode, or 3 group scan mode)

Group priority control

● Sample-and-hold function

Common sample-and-hold circuit included

In addition, channel-dedicated sample-and-hold function (3 channels: in unit 0 only)

included

● Sampling variable

Sampling time can be set up for each channel

● Double trigger mode (A/D conversion data duplicated)

● Three ways to start A/D conversion

Software trigger, timer (MTU3, GPT) trigger, external trigger

● Event linking by the ELC

Temperature sensor unit (TSU)

● 1 channel

● Relative precision: ±1°C (typ)

Table 1.10

Hardware accelerator for industrial interfaces

Feature

Functional description

ΔΣ interface (DSMIF)

● 3 channels × 2 units

● Selectable 2 inputs (U/V) or 3 inputs (U/V/W)

● Up to 6 ΔΣ modulators are externally connectable

● Sinc filter can be selected as first, second or third order

Trigonometric function unit (TFU)

Calculation of sine, cosine, arctangent, hypot_k (

x2+y2/k)

● Simultaneous calculation of sine and cosine

● Simultaneous calculation of arctangent and hypot_k

Table 1.11

Safety (1 of 2)

Feature

Functional description

Memory protection unit (MPU)

● Cortex-R52 MPU

Two stages MPUs (EL2 and EL1)

24 regions each MPU

● Master MPU

Memory protection for masters except Cortex-R52 (DMAC, USB, Ethernet MAC, CoreSight,

SHOSTIF, PHOSTIF)

Protects important registers from being overwritten for in case a program runs out of control.

CRC calculator (CRC)

● 2 channels

● CRC code generation for arbitrary amounts of data in 8-, 16-, or 32-bit units

● Select any of four generating polynomials:

– X32 + X26 + X23 + X22 + X16 + X12 + X11 + X10 + X8 + X7 + X5 + X4 + X2 + X + 1

(32-Ethernet)

– X32 + X28 + X27 + X26 + X25 + X23 + X22 + X20 + X19 + X18 + X14 + X13 + X11 + X10 +

X9 + X8 + X6 + 1 (CRC-32C)

– X16 + X15 + X2 + 1 (CRC-16)

– X16 + X12 + X5 + 1 (CRC-CCITT)

– X8 + X2 + X + 1 (CRC-8)

Clock monitor circuit (CLMA)

● Monitors the abnormal output clock frequency from the PLL circuit or low-speed on-chip

oscillator.

● Input clock oscillation stop detection: Available

Data operation circuit (DOC)

The function to compare, add, or subtract 16-bit data

RZ/N2L Datasheet

1. Overview

R01DS0397EJ0140 Rev.1.40

Mar 31, 2026

Page 8 of 128

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