RZSLASHN2L datasheet(9/128 Pages) RENESAS

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Table 1.11

Safety (2 of 2)

Feature

Functional description

Isolated peripherals

● Safety dedicated peripherals are available:

– GPT: 4 ch

– SCI: 1 ch

– IIC: 1 ch

– SPI: 1 ch

– CRC: 1 unit

– RTC: 1 unit

– GPIO: Sharable with normal GPIO

– On-chip system SRAM with ECC

● They are mapped independently from normal peripherals so that access protection can be

done by EL2 MPU.

Table 1.12

Security

Feature

Functional description

Security*1

● Secure boot

● JTAG authentication*2

● SCI/USB boot disable

● Cryptographic accelerators

– Symmetric Cipher: AES 128/192/256 bits with CBC/ECB/CTR/GCM/XTS

– Asymmetric Cipher: ECC 256 bits, RSA 1024/2048/3072 bits, RSAES-OAEP

– Hash: SHA-1, SHA-2

– Message authentication: HMAC, CMAC, GMAC

– Signature algorithms: ECDSA with NIST P-256, RSASSA-PSS, RSASSA-PKCS1

● TRNG

Note 1. For details, contact our sales representative.

Note 2. Authentication by plaintext is available in non-security support product.

Table 1.13

Debug

Feature

Functional description

Debugging interface

● CoreSight architecture designed by Arm

● Debugging function by the JTAG/SWD interface, and trace function by the trace port

interface

Table 1.14

External host interface

Feature

Functional description

Serial host interface (SHOSTIF)

● Serial communication is possible in slave mode.

● Supported interface

– Motorola Serial Peripheral Interface (4-wire SPI)

– Enhanced SPI Modes with Dual, Quad, or Octal SPI

● Serial clock polarity switching

● Serial clock phase switching

● Single Data Transfer

● Data size is up to 32 bits × 64 burst

Parallel host interface (PHOSTIF)

● Synchronous/Asynchronous SRAM Interface Mode

● Synchronous Burst SRAM Type Transfer Mode

● Bus width: 8 or 16 bits

● Synchronous relations

– HCKIO synchronous

● Write buffer

● Read buffer

● Multiplexing of addresses and data (Synchronous Burst SRAM Type only)

Mailbox and semaphore (MBXSEM)

● Eight semaphores

● Four 32-bit mailboxes for both external host CPU to Cortex-R52 and Cortex-R52 to external

host CPU

● Interrupts can be generated and cleared from both external host CPU and Cortex-R52

RZ/N2L Datasheet

1. Overview

R01DS0397EJ0140 Rev.1.40

Mar 31, 2026

Page 9 of 128

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