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ST20-C1 Datasheet(PDF) 73 Page - STMicroelectronics |
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ST20-C1 Datasheet(HTML) 73 Page - STMicroelectronics |
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73 / 205 page ![]() 73/205 6 Exceptions ® bit 0 of the descriptor, and so can be either ExceptionProcessType (which has the value 1) or UserProcessType (which has the value 0). The type allows each exception level to be assigned to one of the following: • an exception handler. The entry for an exception handler is the address of the exception control block (as described in section 6.3) bitwise ORed with ExceptionProcessType to indicate an exception. • a user process waiting for a peripheral (as described in section 4.11).The entry for a user process is the task descriptor (i.e. the address of the process control block) bitwise ORed with UserProcessType to indicate a user process. • the null entry NotProcess. The CPU treats null entries as disabled exceptions. When the exception is triggered, the CPU looks in the table entry for the requested exception level. If the value in the table is NotProcess then no exception or trap is taken and the CPU continues with the default behavior. Otherwise, if bit 0 is UserProcessType then the address part of the value is assumed to be a valid task descriptor of a process. If bit 0 is ExceptionProcessType, then the address part is assumed to be a pointer to a valid exception control block. Using user processes as exceptions to handle peripherals is described in section 4.11. The rest of this chapter refers only to exceptions. Typically a separate descriptor is used for each interrupt level and system call, so that this scheme provides a system of vectored interrupts and system calls. The exception handler is then executed, and can itself be interrupted or trapped. 6.3 Exception control block and the saved state When an exception is taken, the state is saved in the exception control block. The evaluation stack, status register, Iptr, Wptr and Tdesc are automatically saved on taking the exception and restored on returning. This is done to enable any exception handler to have direct access to the state of the underlying process and is required for some software scheduler implementations. The constants in Table 6.3 define the locations in the control block. Word offset Name Purpose 7 ex.HandlerIptr Exception handler instruction pointer. 6 ex.InterptdStatus Interrupted or trapped process status register. 5 ex.InterptdTdesc Interrupted or trapped process task descriptor. 4 ex.InterptdIptr Interrupted or trapped process instruction pointer. 3 ex.InterptdWptr Interrupted or trapped process workspace pointer. 2 ex.InterptdCreg Interrupted or trapped process Creg. 1 ex.InterptdBreg Interrupted or trapped process Breg. 0 ex.InterptdAreg Interrupted or trapped process Areg. Table 6.3 Exception control block |
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