ST20-C1 datasheet(9/205 Pages) STMICROELECTRONICS

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2 Notation

2.2.1

The process state

The process state consists of the registers (Areg, Breg, Creg, Iptr, Tdesc, Wptr, and

Status), and the contents of memory. A description of the meanings and uses of the

registers and special memory locations and data structures is given in section 3.3.

2.2.2

General

The instruction descriptions are not intended to describe the way the instructions are

implemented, but only their effect on the state of the processor. So, for example, the

result of

mul is shown in terms of an intermediate result calculated to infinite precision,

although no such intermediate result is used in the implementation.

Comments (in

italics) are used to both clarify the description and to describe actions

or values that cannot easily be represented by the notation used here; e.g.

take

timeslice trap. Some of these actions and values are described in more detail in other

chapters.

An ellipsis is used to show a range of values; e.g. ‘i = 0..31’ means that i has values

from 0 to 31, inclusive.

Subscripts are used to indicate particular bits in a word; e.g. Aregi for bit i of Areg; and

Areg0..7 for the least significant byte of Areg. Note that bit 0 is the least significant bit

in a word, and bit 31 is the most significant bit.

Except for Iptr, certain reserved words of memory, and taking exceptions or switching

processes, if the description does not mention the state of a register or memory

location after the instruction, then the value will not be changed by the instruction.

Iptr is assigned the address of the next instruction in the code

before the instruction

execution starts. The Iptr is included in the description only when there are additional

effects of the instruction (e.g. in the

jump instruction). In these cases the address of

the next instruction is indicated by the comment ‘

next instruction’.

2.2.3

Undefined v alues

Some instructions in some circumstances leave the contents of a register or memory

location in an undefined state . This means that the value of the location may be

changed by the instruction, but the new value cannot be easily defined, or is not a

meaningful result of the instruction. For example, when division by zero is attempted,

Breg and Creg become undefined, i.e. they do not contain any meaningful data. An

undefined v alue is represented by the name

undefined.

The values of registers which become undefined as a result of executing an instruc-

tion are implementation dependent and are not guaranteed to be the same on

different members or revisions of the ST20 family of processors.

2.2.4

Data types

The instruction set includes operations on three sizes of data: 8, 16 and 32-bit objects.

8-bit and 16-bit data can represent signed or unsigned integers and 32-bit data can

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