ISPCLOCK5600A datasheet(39/51 Pages) LATTICE

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Lattice Semiconductor

ispClock5600A Family Data Sheet

1-39

For ispClock5600A, the instruction word length is eight bits. All ispClock5600A instructions available to users are

shown in Table 1-6.

The following table lists the instructions supported by the ispClock5600A JTAG Test Access Port (TAP) controller:

Table 1-6. ispClock5600A TAP Instruction Table

BYPASS is one of the three required instructions. It selects the Bypass Register to be connected between TDI and

TDO and allows serial data to be transferred through the device without affecting the operation of the

ispClock5600A. The IEEE 1149.1 standard deﬁnes the bit code of this instruction to be all ones (111111).

The required SAMPLE/PRELOAD instruction dictates the Boundary-Scan Register be connected between TDI

and TDO. The bit code for this instruction is deﬁned by Lattice as shown in Table 1-6.

The EXTEST (external test) instruction is required and will place the device into an external boundary test mode

while also enabling the boundary scan register to be connected between TDI and TDO. The bit code of this instruc-

tion is deﬁned by the 1149.1 standard to be all zeros (000000).

The optional IDCODE (identiﬁcation code) instruction is incorporated in the ispClock5600A and leaves it in its func-

tional mode when executed. It selects the Device Identiﬁcation Register to be connected between TDI and TDO.

The Identiﬁcation Register is a 32-bit shift register containing information regarding the IC manufacturer, device

type and version code (Figure 1-33). Access to the Identiﬁcation Register is immediately available, via a TAP data

scan operation, after power-up of the device, or by issuing a Test-Logic-Reset instruction. The bit code for this

instruction is deﬁned by Lattice as shown in Table 1-6.

Instruction

Code

Description

EXTEST

0000 0000

External Test.

ADDRESS_SHIFT

0000 0001

Address register (10 bits)

DATA_SHIFT

0000 0010

Address column data register (89 bits)

BULK_ERASE

0000 0011

Bulk Erase

PROGRAM

0000 0111

Program column data register to E

PROGRAM_SECURITY

0000 1001

Program Electronic Security Fuse

VERIFY

0000 1010

Verify column

DISCHARGE

0001 0100

Fast VPP Discharge

PROGRAM_ENABLE

0001 0101

Enable Program Mode

IDCODE

0001 0110

Address Manufacturer ID code register (32 bits)

USERCODE

0001 0111

Read UES data from E

2 and addresses UES register (32 bits)

PROGRAM_USERCODE

0001 1010

Program UES register into E

PROGRAM_DISABLE

0001 1110

Disable Program Mode

HIGHZ

0001 1000

Force all outputs to High-Z state

SAMPLE/PRELOAD

0001 1100

Capture current state of pins to boundary scan register

CLAMP

0010 0000

Drive I/Os with boundary scan register

INTEST

0010 1100

Performs in-circuit functional testing of device.

ERASE DONE

0010 0100

Erases the ‘Done’ bit only

PROG_INCR

0010 0111

Program column data register to E

2 and auto-increment address register

VERIFY_INCR

0010 1010

Load column data register from E

2 and auto-increment address register

PROGRAM_DONE

0010 1111

Programs the ‘Done’ Bit

NOOP

0011 0000

Functions Similarly to CLAMP instruction

BYPASS

1xxx xxxx

Bypass - Connect TDO to TDI

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