ISPCLOCK5600A datasheet(13/51 Pages) LATTICE

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Lattice Semiconductor

ispClock5600A Family Data Sheet

1-13

Timing Speciﬁcations

Skew Matching

Programmable Skew Control

Control Functions

Figure 1-7. RESET and Proﬁle Select Timing

Symbol

Parameter

Conditions

Min.

Typ.

Max.

Units

tSKEW

Output-output Skew

Between any two identically conﬁgured and loaded

outputs regardless of bank.

—

Symbol

Parameter

Conditions

Min.

Typ.

Max.

Units

tSKRANGE

Skew Control Range

Fine Skew Mode, fVCO = 320 MHz

—

5.86

—

Fine Skew Mode, fVCO = 800 MHz

—

2.34

—

Coarse Skew Mode, fVCO = 320 MHz

—

11.72

—

Coarse Skew Mode, fVCO = 800 MHz

—

4.68

—

SKSTEPS

Skew Steps per range

—

tSKSTEP

Skew Step Size

Fine Skew Mode, fVCO = 320 MHz

—

390

—

Fine Skew Mode, fVCO = 800 MHz

—

156

—

Coarse Skew Mode, fVCO = 320 MHz

—

780

—

Coarse Skew Mode, fVCO = 800 MHz

—

312

—

tSKERR

Skew Time Error

Fine skew mode

—

Coarse skew mode

—

1. Skew control range is a function of VCO frequency (fVCO). In ﬁne skew mode TSKRANGE = 15/(8 x fVCO).

In coarse skew mode TSKRANGE = 15/(4 x fVCO).

2. Skew step size is a function of VCO frequency (fVCO). In ﬁne skew mode TSKSTEP = 1/(8 x fVCO).

In coarse skew mode TSKSTEP = 1/(4 x fVCO).

3. Only applicable to outputs with non-zero skew settings.

Symbol

Parameter

Conditions

Min.

Typ.

Max.

Units

tDIS/OE

Delay Time, OEX or OEY to Output Disabled/

Enabled

—10

tDIS/GOE

Delay Time, GOE to Output Disabled/Enabled

—

tSUSGATE

Setup Time, SGATE to Output Clock Start/

Stop

—

cycles

tPLL_RSTW

PLL Reset Pulse Width

1—

—

tRSTW

Logic Reset Pulse Width

—

tHPS_RST

Hold time for RESET past change in PS[0..1]

—

1. Output clock cycles for the particular output being controlled.

2. Will completely reset PLL.

3. Will only reset digital logic.

tHPS_RST

tPLL_RSTW

PS[0..1]

RESET

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