ISPCLOCK5600A datasheet(21/51 Pages) LATTICE

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Lattice Semiconductor

ispClock5600A Family Data Sheet

1-21

Figure 1-14. ispClock5600A Clock Reference and Feedback Input Structure (REFA+/- Pair Shown)

The following usage guidelines are suggested for interfacing to supported logic families.

LVTTL (3.3V), LVCMOS (1.8V, 2.5V, 3.3V)

The receiver should be set to LVCMOS or LVTTL mode, and the input signal should be connected to the ‘+’ termi-

nal of the input pair (e.g. REFA+). The ‘-’ input terminal should be connected to GND. In addition, REFVTT should

also be tied to GND. CMOS transmission lines are generally source terminated, so all termination resistors should

be set to the OPEN state. Figure 1-15 shows the proper conﬁguration. Please note that because switching thresh-

olds are different for LVCMOS running at 1.8V, there is a separate conﬁguration setting for this particular standard.

Figure 1-15. LVCMOS/LVTTL Input Receiver Conﬁguration

HSTL, eHSTL, SSTL2, SSTL3

The receiver should be set to HSTL/SSTL mode, and the input signal should be fed into the ‘+’ terminal of the input

pair. The ‘-’ input terminal should be tied to the appropriate VREF value, and the associated REFVTT or FBKVTT

terminal should be tied to a VTT termination supply. The positive input’s terminating resistor should be engaged and

set to 50Ω. Figure 1-16 shows an appropriate conﬁguration. Refer to the “Recommended Operating Conditions -

Supported Logic Standards” table in this data sheet for suitable values of VREF and VTT. If one of the REF or FBK

REFA-

REFA+

REFVTT

To Internal

Logic

Single-ended

ispClock5600A

Receiver

Differential

Receiver

OPEN

REFA+

REFA-

REFVTT

Single-ended

Receiver

GND

Signal In

ispClock5600A

ISPCLOCK5600A Datasheet(PDF) 21 Page - Lattice Semiconductor