ISPCLOCK5600A datasheet(9/51 Pages) LATTICE

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Lattice Semiconductor

ispClock5600A Family Data Sheet

1-9

Output Rise and Fall Times – Typical Values

1, 2

Output Test Loads

Figures 1-3-1-5 show the equivalent termination loads used to measure rise/fall times, output timing adders and

other selected parameters as noted in the various tables of this data sheet.

Figure 1-3. CMOS Termination Load

Figure 1-4. eHSTL/HSTL/SSTL Termination Load

Output Type

Slew 1 (Fastest)

Slew 2

Slew 3

Slew 4 (Slowest)

Units

LVTTL

0.54

0.76

0.60

0.87

0.78

1.26

1.05

1.88

LVCMOS 1.8V

0.75

0.69

0.88

0.78

0.83

1.11

1.20

1.68

LVCMOS 2.5V

0.57

0.69

0.65

0.78

0.99

0.98

1.65

1.51

LVCMOS 3.3V

0.55

0.77

0.60

0.87

0.78

1.26

1.05

1.88

SSTL18

0.55

0.40

——————

SSTL2

0.50

0.40

——————

SSTL3

0.50

0.45

——————

HSTL

0.60

0.45

——————

eHSTL

0.55

0.40

——————

LVDS

0.25

0.20

——————

LVPECL

0.20

——————

1. See Figures 1-3-1-5 for test conditions.

2. Measured between 20% and 80% points.

3. Only the ‘fastest’ slew rate is available in LVDS and LVPECL modes.

ispClock

SCOPE

950Ω

50Ω/3"

50Ω/36"

50Ω 5pF

Zo = 50Ω

ispCLOCK

SCOPE

50Ω/3"

50Ω/36"

950Ω

50Ω 5pF

Zo = HSTL: ~20Ω

SSTL: 40Ω

VTERM

50Ω

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