TS68HC901 datasheet(9/42 Pages) STMICROELECTRONICS

9 / 42 page

INTERRUPT STRUCTURE

In a 68000 system, the CMFP will be assigned to

one of the seven possible interrupt levels. All inter-

rupt service requests from the CMFP’s 16 interrupt

channels will be presented at this level. Although, as

an interrupt controller, the CMFP will internally prio-

ritize its 16 interrupt sources. Additional interrupt

sources may be placed at the same interrupt level

by daisy-chaining multiple CMFPs. The CMFPs will

be prioritized by their position in the chain.

INTERRUPT PROCESSING

Each CMFP provides individual interrupt capability

for its various functions. When an interrupt is recei-

ved on one of the external interrupt channels or from

one of the eight internal sources, the CMFP will re-

quest interrupt service. The 16 interrupt channels

are assigned a fixed priority so that multiple pending

interrupts are serviced according to their relative im-

portance. Since the CMFP can internally generate

16 vector numbers, the unique vector number which

corresponds to the highest priority channel that as

a pending interrupt is presented to the processor du-

ring an interrupt acknowledge cycle. This unique

vector number allows the processor to immediately

begin execution of the interrupt handler for the inter-

rupt source, decreasing interrupt latency time.

INTERRUPT CHANNEL PRIORITIZATION

The 16 interrupt channels are prioritized as shown

in figure 5. General purpose interrupt 7 (I7) is the hi-

ghest priority interrupt channel and I0 is the lowest

priority channel. Pending interrupts are presented to

the CPU in order of priority unless they have been

masked off. By selectively masking interrupts, the

channel are in effect re-prioritized.

INTERRUPT VECTOR NUMBER FORMAT

During an interrupt acknowledge cycle, a unique 8-

bit vector number is presented to the system which

corresponds to the specific interrupt source which is

requesting service. The format of the vector is

shown in figure 6. The most significant four bits of

the interrupt vector number are user programmable.

These bits are set by writing the upper four bits of

the vector register which is shown in figure 7. The

low order bits are generated internally by the

TS68HC901. Note that the binary channel number

shown in figure 5 corresponds to the low order bits

of the vector number associated with each channel.

Figure 9 : Interrupt Channel

Prioritization

Priority

Channel

Description

HIGHEST

LOWEST

1111

1110

1101

1100

1011

1010

1001

1000

0111

0110

0101

0100

0011

0010

0001

0000

General Purpose Interrupt 7(I7)

General Purpose Interrupt 6(I6)

Timer A

Receive Buffer Full

Receive Error

Transmit Buffer Empty

Transmit Error

Timer B

General Purpose Interrupt 5(I5)

General Purpose Interrupt 4(I4)

Timer C

Timer D

General Purpose Interrupt 3(I3)

General Purpose Interrupt 2(I2)

General Purpose Interrupt 1(I1)

General Purpose Interrupt 0(I0)

Figure 5 : Interrupt Channel Prioritization

TS68HC901

9/42

TS68HC901 Datasheet(PDF) 9 Page - STMicroelectronics

TS68HC901 Datasheet(HTML) 9 Page - STMicroelectronics

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42

Datasheet Download

Link URL