TS68HC901 datasheet(15/42 Pages) STMICROELECTRONICS

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GENERAL PURPOSE INPUT/OUTPUT

INTERRUPT PORT

The general purpose interrupt input/output (I/O) port

(GPIP) provides eight I/O lines (I0 through I7) that

may be operated as either inputs or outputs under

software control. In addition, these lines may optio-

nally generate an interrupt on either a positive trans-

ition or negative transition of the input signal. The

flexibility of the GPIP allows it to be configured as an

8-Bit I/0 port or for bit I/O. Since interrupts are en-

abled on a bit-by-bit basis, a subset of the GPIP

could be programmed as handshake lines or the

port could be connected to as many as eight exter-

nal interrupt sources, which would be prioritized by

the CMFP interrupt controller for interrupt service.

6800 INTERRUPT CONTROLLER

The CMFP interrupt controller is particularly useful

in a system which has many 6800-type devices. Ty-

pically, in a vectored 68000 system, 6800-type pe-

ripherals use the autovector which corresponds to

their assigned interrupt level since they do not pro-

vide a vector number in response to an AC cycle.

The autovector interrupt handler must then poll all

6800-type devices at that interrupt level to deter-

mine which device is requesting service. However,

by tying the IRQ output from a 6800-type device to

the general purpose I/O interrupt port (GPIP) of a

CMFP, a unique vector number will be provided to

the processor during an interrupt acknowledge cy-

cle. This interrupt structure will significantly reduce

interrupt latency for 6800-type devices and other pe-

ripheral devices which do not support vector-by-de-

vice.

GPIP CONTROL REGISTERS

The GPIP is programmed via three control registers

shown in figure 11. These registers control the data

direction provide user access to the port, and specify

the active edge for each bit of the GPIP which will

produce an interrupt. These registers are described

in detail in the following paragraphs.

GPIP DATA REGISTER

The general purpose I/O data register is used to in-

put or output data to the port. When data is written

to the GPIP data register, those pins which are de-

fined as inputs will remain in the high-impedance

state. Pins which are defined as outputs will assume

the state (high or low) of their corresponding bit in

the data register. When the GPIP is read, data will

be passed directly from the bits of the data register

for pins which are defined as outputs. Data from pins

defined as inputs will come from the input buffers.

ACTIVE EDGE REGISTER

The active edge register (AER) allows each of the

GPIP lines to produce an interrupt on either a one-

to-zero or a zero-to-one transition. Writing a zero the

appropriate edge bit of the active edge register

causes the associated input to generate an interrupt

on the one-to-zero transition. Writing a one to the

edge bit will produce an interrupt on the zero-to-one

transition of the corresponding GPIP line.

TS68HC901

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