TS68HC901 datasheet(14/42 Pages) STMICROELECTRONICS

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NESTING CMFP INTERRUPTS

In a 68000 vectored interrupt system, the CMFP is

assigned to one of seven possible interrupt levels.

When an interrupt is received from the CMFP, an in-

terrupt acknowledge for that level is initiated. Once

an interrupt is recognized at a particular level, inter-

rupts at that same level or below are masked by

68000. As long as the processor’s interrupt mask is

unchanged, the 68000 interrupt structure will prohi-

bit the nesting of interrupts at the same interrupt le-

vel. However, additional interrupt requests from the

CMFP can be recognized before a previous chan-

nel’s interrupt service routine is completed by lowe-

ring the processor’s interrupt mask to the next lower

interrupt level within the interrupt handler.

When nesting CMFP interrupts, it may be desirable

to permit interrupts on any CMFP channel, regar-

dless of its priority, to preempt or delay interrupt pro-

cessing of an earlier channel’s interrupt service re-

quest. Or, it may be desirable to only allow sub-

sequent higher priority channel interrupt requests to

supersede previously recognized lower priority in-

terrupt requests. The CMFP interrupt structure pro-

vides this flexibility by offering two end-of-interrupt

options for vectored interrupt schemes. Note that

the end-of-interrupt modes are not active in a polled

interrupt scheme.

SELECTING THE END-OF-INTERRUPT MODE

In a vectored interrupt scheme, the CMFP may be

programmed to operate in either the automatic end-

of-interrupt mode or the software end-of-interrupt

mode. The mode is selected by writing the S bit of

the vector register (see figure 7). When the S bit is

programmed to a one, the CMFP is placed in the

software end-of-interrupt mode and when the S bit

is a zero, all channels operate in the automatic end-

of-interrupt mode.

AUTOMATIC END-OF-INTERRUPT

When an interrupt vector number is passed to the

processor during an interrupt acknowledge cycle,

the corresponding channel’s interrupt pending bit is

cleared. In the automatic end-of-interrupt mode, no

further history of the interrupt remains in the CMFP.

The in-service bits of the interrupt in-service regis-

ters (ISRA and ISRB) are forced low. Subsequent

interrupts which are received on any CMFP channel

will generate an interrupt request to the processor,

even if the current interrupt’s service routine has not

been completed.

SOFTWARE END-OF-INTERRUPT

In the software end-of-interrupt mode, the channel’s

associated interrupt pending bit is cleared and in ad-

dition, the channel’s in-service bit of in-service regis-

ter A or B is set when its vector number is passed

to the processor during an IACK cycle. A higher prio-

rity channel may subsequently request interrupt ser-

vice and be acknowledged, but as long as the chan-

nel’s in-service bit is set, no lower priority channel

may request interrupt service nor pass its vector du-

ring an interrupt acknowledge sequence.

While only higher priority channels may request in-

terrupt service, any channel can receive an interrupt

and set its interrupt pending bit. Even the channel

whose in-service bit is set can receive a second in-

terrupt. However, no interrupt service request is

made until its in-service bit is cleared.

The in-service bit for a particular channel can be

cleared by writing a zero to its corresponding bit in

ISRA or ISRB and ones to all other bit positions.

Since bits in the in-service registers can only be

cleared in software and not set, writing ones to the

ISRB may be read at any time.

TS68HC901

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