TS68HC901 datasheet(24/42 Pages) STMICROELECTRONICS

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the user must determine the synchronous word pa-

rity and write it into synchronous character. The

CMFP will then transmit the extra bit in the synchro-

nous word as a parity bit.

USART CONTROL REGISTER

The USART control register (UCR) selects the clock

mode and the character format for the receive and

transmit sections. This register is shown in Fig-

ure 17.

RECEIVER

As data is received on the serial input line (SI), it is

clocked into an internal 8-bit shift register until the

specified number of data bits have been assembled.

This character will then be transferred to the receive

buffer, assuming that the last word in the receiver

buffer has been read. This transfer produces a buff-

er full interrupt to the processor.

Reading the receive buffer satisfies the buffer full

condition and allows a next data word to be trans-

ferred to the receive buffer when it is assembled.

The receive buffer is accessed by reading the U-

SART data register (UDR). The UDR is simply an 8-

bit data register used when transferring data from

the CMFP and CPU.

Each time a word is transferred to the receive buffer,

its status information is latched into the receiver sta-

tus register (RSR). The RSR is not updated again

until the data word in the receive buffer has been

read. When a buffer full condition exists, the RSR

should always be read before the receive buffer

(UDR) to maintain the correct correspondence be-

tween data and flags. Otherwise, it is possible that

after reading the UDR and prior to reading the RSR,

a new word could be receive and transferred to the

USART CONTROL REGISTER

UCR

(29h)

CLK

WL1

WL0

ST1

ST0

E/O

CLEARED on RESE T

Wr iting 0 : CLEARED

Wri ting 1 : SET

Figure 17 :

receive buffer. Its associated flags would be latched into the RSR, over-writing the flags of the previous

data word. Then when the RSR were read to access the status information for the first data word, the

flags for the new word would be retrieved.

CLK

Clock Mode. When this bit is zero, data will be clocked into and out of the receiver and trans-

mitter at the frequency of their respective clocks. When this bit is a one, data will be clocked

into and out of the receiver and transmitter at one sixteenth the frequency of their respective

clocks. Also, the receiver data transition resynchronization logic will be enabled.

WL0, WL1 Word Length. These two bits specify the length of the data word exclusive of start bits, stop

bits, and parity.

ST0, ST1 Start/Stop Bit and Format Control. These two bits select the number of start and stop bits

and also specify the character format.

Parity Enable. When this bit is zero, no parity check will be made and no parity bit will be

computed for transmission. When this bit is a one, parity will be checked by the receiver and

parity will be calculated and inserted during data transmission. Note that parity is not auto-

matically appended to the synchronous character for word lengths of less than eight bits. In

this case, the parity should be written into the synchronous character register along with the

synchronous word.

E/0

Even/Odd Parity. When this bit is zero, odd parity is selected. When this bit is a one, even

parity is selected.

Bit 0 Reserved. Must be maintained at 0.

ST1

ST0

Start Bits

Stop Bits

Format

WL1

WL0

Word Length

TS68HC901

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