TS68HC901 datasheet(30/42 Pages) STMICROELECTRONICS

30 / 42 page

AC ELECTRICAL CHARACTERISTICS (VCC = 5.0Vdc ± 5%, GND = 0Vdc, TA =0°Cto 70°C)

Number

Characteristic

Value

Unit

4MHz

5MHz

8MHz

Min.

Max.

Min.

Max.

Min.

Max.

CS, DS Width High

R/W, A1-A5 Valid to Falling CS (setup)

Data Valid Prior to Falling CLK

280

150

100

4(3)

CS, IACK Valid to Falling Clock (setup)

4a(4)

Falling Clock to Next CS Low

100

CLK Low to DTACK Low

220

180

CS, DS or IACK High to DTACK High

CS, DS or IACK High to DTACK Tri-state

100

DTACK Low to Data Invalid (hold time)

CS, DS or IACK High to Data Tri-state

CS or DS High to R/W, A1-A5 Invalid

(hold time)

000

11(3,5)

Data Valid from CS Low

310

260

200

Read Data Valid to DTACK Low (setup)

DTACK Low to DS, CS or IACK High

(hold time)

000

IEI Low to Falling CLK (setup)

15(1)

IEO Valid from Clock Low (delay)

180

120

Data Valid from Clock Low (delay)

300

180

IEO Invalid from IACK High (delay)

150

100

DTACK Low from Clock High (delay)

180

165

100

19(1)

IEO Valid from IEI Low (delay)

100

Data Valid from IEI Low (delay)

220

195

Clock Cycle Time

250

1000

200

1000

125

1000

Clock Width Low

110

Clock Width High

110

24(4)

DS Inactive to rising Clock (setup)

100

I/O Minimum Active Pulse Width

100

IACK Width High

TCLK

I/O Data Valid from Rising CS or DS

450

350

Receiver Ready Delay from Rising RC

600

200

Transmitter Ready Delay from Rising TC

600

200

Not es :

1. IEO only goes low if no acknowledgeable interrupt is

pending. If IEO goes low, DTACK and the data bus re-

main tri-stated.

2. TCLK refers to the clock applied to the MFP CLK input

pin. tCLK refers to the timer clock signal, regardless of

whetherthat signal comes from the XTAL 1/XTAL2 crys-

tal clock inputs or the TAI or TBI timer inputs.

3. If the setup time is not met, CS or IACK will not be reco-

gnized until the next falling CLK.

4. If this setup time is met (for consecutive cycles), the mi-

nimum hold-off time of one clock cycle will be obtained.

If not met, the hold-off will be two clock cycles.

5. Although CS and DTACK are synchronized with the

clock, the data out during a read cycle is asynchronous

to the clock, relying only on CS for timing.

6. Spec. 30 applies to timer outputs TAO and TBO only.

TS68HC901

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