56F8167 datasheet(86/182 Pages) FREESCALE

86 / 182 page

56F8367 Technical Data, Rev. 9

Freescale Semiconductor

Preliminary

5.6.1

Interrupt Priority Register 0 (IPR0)

Figure 5-3 Interrupt Priority Register 0 (IPR0)

5.6.1.1

Reserved—Bits 15–14

This bit field is reserved or not implemented. It is read as 0 and cannot be modified by writing.

5.6.1.2

EOnCE Breakpoint Unit 0 Interrupt Priority Level (BKPT_U0 IPL)—

Bits13–12

This field is used to set the interrupt priority levels for IRQs. This IRQ is limited to priorities 1 through 3.

It is disabled by default.

•

00 = IRQ disabled (default)

•

01 = IRQ is priority level 1

•

10 = IRQ is priority level 2

•

11 = IRQ is priority level 3

5.6.1.3

EOnCE Step Counter Interrupt Priority Level (STPCNT IPL)— Bits 11–10

This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 1 through 3.

It is disabled by default.

•

00 = IRQ disabled (default)

•

01 = IRQ is priority level 1

•

10 = IRQ is priority level 2

•

11 = IRQ is priority level 3

5.6.1.4

Reserved—Bits 9–0

This bit field is reserved or not implemented. It is read as 0 and cannot be modified by writing.

5.6.2

Interrupt Priority Register 1 (IPR1)

Figure 5-4 Interrupt Priority Register 1 (IPR1)

Base + $0

Read

BKPT_U0IPL

STPCNT IPL

Write

RESET

000

Base + $1

Read

RX_REG IPL

TX_REG IPL

TRBUF IPL

Write

RESET

000000

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