56F8167 datasheet(20/182 Pages) FREESCALE

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56F8367 Technical Data, Rev. 9

Freescale Semiconductor

Preliminary

XTAL

K12

Input/

Output

Chip-driven Crystal Oscillator Output — This output connects the internal

crystal oscillator output to an external crystal.

If an external clock is used, XTAL must be used as the input and

EXTAL connected to GND.

The input clock can be selected to provide the clock directly to the

core. This input clock can also be selected as the input clock for

the on-chip PLL.

CLKO

Output

In reset,

output is

disabled

Clock Output — This pin outputs a buffered clock signal. Using

the SIM CLKO Select Register (SIM_CLKOSR), this pin can be

programmed as any of the following: disabled, CLK_MSTR

(system clock), IPBus clock, oscillator output, prescaler clock and

postscaler clock. Other signals are also available for test

purposes.

See Part 6.5.7 for details.

(GPIOA8)

154

Output

Input/

Output

In reset,

output is

disabled,

pull-up is

enabled

Address Bus — A0 - A5 specify six of the address lines for

external program or data memory accesses.

Depending upon the state of the DRV bit in the EMI bus control

the external bus is inactive.

Most designs will want to change the DRV state to DRV = 1 instead

of using the default setting.

Port A GPIO — These six GPIO pins can be individually

programmed as input or output pins.

After reset, the default state is Address Bus.

To deactivate the internal pull-up resistor, clear the appropriate

GPIO bit in the GPIOA_PUR register.

Example: GPIOA8, clear bit 8 in the GPIOA_PUR register.

(GPIOA9)

(GPIOA10)

(GPIOA11)

(GPIOA12)

(GPIOA13)

Table 2-2 Signal and Package Information for the 160-Pin LQFP and MBGA (Continued)

Signal

Name

No.

Ball No.

Type

State

During

Reset

Signal Description

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