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56F8167 Datasheet(PDF) 94 Page - Freescale Semiconductor, Inc |
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56F8167 Datasheet(HTML) 94 Page - Freescale Semiconductor, Inc |
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94 / 182 page  56F8367 Technical Data, Rev. 9 94 Freescale Semiconductor Preliminary 5.6.6.5 Reserved—Bits 7–6 This bit field is reserved or not implemented. It is read as 0 and cannot be modified by writing. 5.6.6.6 SCI1 Transmitter Idle Interrupt Priority Level (SCI1_TIDL IPL)—Bits 5–4 This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2. They are disabled by default. • 00 = IRQ disabled (default) • 01 = IRQ is priority level 0 • 10 = IRQ is priority level 1 • 11 = IRQ is priority level 2 5.6.6.7 SCI1 Transmitter Empty Interrupt Priority Level (SCI1_XMIT IPL)— Bits 3–2 This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2. They are disabled by default. • 00 = IRQ disabled (default) • 01 = IRQ is priority level 0 • 10 = IRQ is priority level 1 • 11 = IRQ is priority level 2 5.6.6.8 SPI0 Transmitter Empty Interrupt Priority Level (SPI_XMIT IPL)— Bits 1–0 This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2. They are disabled by default. • 00 = IRQ disabled (default) • 01 = IRQ is priority level 0 • 10 = IRQ is priority level 1 • 11 = IRQ is priority level 2 5.6.7 Interrupt Priority Register 6 (IPR6) Figure 5-9 Interrupt Priority Register 6 (IPR6) Base + $6 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Read TMRC0 IPL TMRD3 IPL TMRD2 IPL TMRD1 IPL TMRD0 IPL 0 0 DEC0_XIRQ IPL DEC0_HIRQ IPL Write RESET 00000 0000000 0000 |
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