PCF2123TS datasheet(32/55 Pages) NXP

32 / 55 page

PCF2123_2

Product data sheet

Rev. 02 — 4 December 2009

32 of 55

NXP Semiconductors

PCF2123

SPI Real time clock/calendar

[1]

F0 is clocked at 32.768 kHz.

9.14 3-line serial interface

Data transfer to and from the device is made via a 3-wire SPI-bus (see Table 41). The

data lines for input and output are split. The data input and output lines can be connected

together to facilitate a bidirectional data bus. The chip enable signal is used to identify the

transmitted data. Each data transfer is a byte, with the Most Signiﬁcant Bit (MSB) sent ﬁrst

(see Figure 24).

Table 40.

First increment of time circuits after STOP bit release

Bit

Prescaler bits

[1]

1 Hz tick

Time

Comment

STOP

F0F1-F2 to F14

hh:mm:ss

Clock is running normally

01-0 0001 1101 0100

12:45:12

prescaler counting normally

STOP bit is activated by user. F0F1 are not reset and values cannot be predicted externally

XX-0 0000 0000 0000

12:45:12

prescaler is reset; time circuits are frozen

New time is set by user

XX-0 0000 0000 0000

08:00:00

prescaler is reset; time circuits are frozen

STOP bit is released by user

XX-0 0000 0000 0000

08:00:00

prescaler is now running

XX-1 0000 0000 0000

08:00:00

XX-0 1000 0000 0000

08:00:00

XX-1 1000 0000 0000

08:00:00

11-1 1111 1111 1110

08:00:00

00-0 0000 0000 0001

08:00:01

0 to 1 transition of F14 increments the time circuits

10-0 0000 0000 0001

08:00:01

11-1 1111 1111 1111

08:00:01

00-0 0000 0000 0000

08:00:01

10-0 0000 0000 0000

08:00:01

11-1 1111 1111 1110

08:00:01

00-0 0000 0000 0001

08:00:02

0 to 1 transition of F14 increments the time circuits

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